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tilelink2: move TL-specific stuff out of the LazyModule base classes

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This commit is contained in:
Wesley W. Terpstra 2016-08-31 10:37:30 -07:00
parent f99a3dbec7
commit 8d54ae8508
2 changed files with 25 additions and 25 deletions
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16
uncore/src/main/scala/tilelink2/Bases.scala
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@ -8,11 +8,10 @@ import chisel3.internal.sourceinfo.SourceInfo
abstract class LazyModule
{
private val bindings = ListBuffer[(TLBaseNode, Int, TLBaseNode, Int, SourceInfo)]()
private val bindings = ListBuffer[() => Unit]()
def tl(manager: TLBaseNode, client: TLBaseNode)(implicit sourceInfo: SourceInfo) = {
val (i, j) = manager.edge(client)
bindings += ((manager, i, client, j, sourceInfo))
bindings += manager.edge(client)
}
def module: LazyModuleImp
@ -28,16 +27,7 @@ abstract class LazyModule
m.invoke(this).asInstanceOf[LazyModule].module
}
}
bindings.foreach { case (x, i, y, j, s) =>
val in = x.connectIn(i)
val out = y.connectOut(j)
TLMonitor.legalize(out, y.edgesOut(j), in, x.edgesIn(i), s)
in.<>(out)(s)
val mask = ~UInt(x.edgesIn(i).manager.beatBytes - 1)
in .a.bits.address.:=(mask & out.a.bits.address)(s)
out.b.bits.address.:=(mask & in .b.bits.address)(s)
in .c.bits.address.:=(mask & out.c.bits.address)(s)
}
bindings.foreach { f => f () }
}
}

34
uncore/src/main/scala/tilelink2/Nodes.scala
View File

@ -4,6 +4,7 @@ package uncore.tilelink2
import Chisel._
import scala.collection.mutable.ListBuffer
import chisel3.internal.sourceinfo.SourceInfo
class TLBaseNode(
private val clientFn: Option[Seq[TLClientPortParameters] => TLClientPortParameters],
@ -28,18 +29,6 @@ class TLBaseNode(
private var clientRealized = false
private var managerRealized = false
protected[tilelink2] def edge(x: TLBaseNode) = {
require (!noManagers)
require (!managerRealized)
require (!x.noClients)
require (!x.clientRealized)
val i = accManagerPorts.size
val j = x.accClientPorts.size
accManagerPorts += x
x.accClientPorts += this
(i, j)
}
private lazy val clientPorts = { clientRealized = true; require (numClientPorts.contains(accClientPorts.size)); accClientPorts.result() }
private lazy val managerPorts = { managerRealized = true; require (numManagerPorts.contains(accManagerPorts.size)); accManagerPorts.result() }
private lazy val clientParams : Option[TLClientPortParameters] = clientFn.map(_(managerPorts.map(_.clientParams.get)))
@ -53,6 +42,27 @@ class TLBaseNode(
def connectOut = bundleOut
def connectIn = bundleIn
protected[tilelink2] def edge(x: TLBaseNode)(implicit sourceInfo: SourceInfo) = {
require (!noManagers)
require (!managerRealized)
require (!x.noClients)
require (!x.clientRealized)
val i = accManagerPorts.size
val j = x.accClientPorts.size
accManagerPorts += x
x.accClientPorts += this
() => {
val in = connectIn(i)
val out = x.connectOut(j)
TLMonitor.legalize(out, x.edgesOut(j), in, edgesIn(i), sourceInfo)
in <> out
val mask = ~UInt(edgesIn(i).manager.beatBytes - 1)
in .a.bits.address := (mask & out.a.bits.address)
out.b.bits.address := (mask & in .b.bits.address)
in .c.bits.address := (mask & out.c.bits.address)
}
}
}
class TLClientNode(