tilelink2: optimize support testing circuits
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@ -136,6 +136,7 @@ case class TLManagerParameters(
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case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes: Int)
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{
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require (!managers.isEmpty)
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require (isPow2(beatBytes))
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// Require disjoint ranges for Ids and addresses
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@ -182,8 +183,10 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
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def containsById(id: UInt) = findById(id).reduce(_ || _)
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private def safety_helper(member: TLManagerParameters => TransferSizes)(address: UInt, lgSize: UInt) = {
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(find(address) zip managers.map(member(_).containsLg(lgSize)))
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.map { case (m, s) => m && s } reduce (_ || _)
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val allSame = managers.map(member(_) == member(managers(0))).reduce(_ && _)
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if (allSame) member(managers(0)).containsLg(lgSize) else {
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Mux1H(find(address), managers.map(member(_).containsLg(lgSize)))
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}
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}
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// Check for support of a given operation at a specific address
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@ -194,8 +197,9 @@ case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes
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val supportsPutFull = safety_helper(_.supportsPutFull) _
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val supportsPutPartial = safety_helper(_.supportsPutPartial) _
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def supportsHint(address: UInt) = {
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(find(address) zip managers.map(_.supportsHint))
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.map { case (m, b) => m && Bool(b) } reduce (_ || _)
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if (allSupportHint) Bool(true) else {
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Mux1H(find(address), managers.map(m => Bool(m.supportsHint)))
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}
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}
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}
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@ -220,6 +224,8 @@ case class TLClientParameters(
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}
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case class TLClientPortParameters(clients: Seq[TLClientParameters]) {
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require (!clients.isEmpty)
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// Require disjoint ranges for Ids
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clients.combinations(2).foreach({ case Seq(x,y) =>
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require (!x.sourceId.overlaps(y.sourceId))
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@ -255,8 +261,10 @@ case class TLClientPortParameters(clients: Seq[TLClientParameters]) {
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def contains(id: UInt) = find(id).reduce(_ || _)
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private def safety_helper(member: TLClientParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
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(find(id) zip clients.map(member(_).containsLg(lgSize)))
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.map { case (m, s) => m && s } reduce (_ || _)
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val allSame = clients.map(member(_) == member(clients(0))).reduce(_ && _)
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if (allSame) member(clients(0)).containsLg(lgSize) else {
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Mux1H(find(id), clients.map(member(_).containsLg(lgSize)))
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}
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}
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// Check for support of a given operation at a specific id
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@ -267,8 +275,9 @@ case class TLClientPortParameters(clients: Seq[TLClientParameters]) {
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val supportsPutFull = safety_helper(_.supportsPutFull) _
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val supportsPutPartial = safety_helper(_.supportsPutPartial) _
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def supportsHint(id: UInt) = {
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(find(id) zip clients.map(_.supportsHint))
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.map { case (m, b) => m && Bool(b) } reduce (_ || _)
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if (allSupportHint) Bool(true) else {
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Mux1H(find(id), clients.map(c => Bool(c.supportsHint)))
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}
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}
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}
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