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debug: add clock crossing primitives

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Wesley W. Terpstra 2016-07-18 14:29:13 -07:00 committed by Howard Mao
parent e406d1bd73
commit fa8317fec1
1 changed files with 18 additions and 0 deletions
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18
uncore/src/main/scala/devices/Debug.scala
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@ -983,3 +983,21 @@ class DebugModule ()(implicit val p:cde.Parameters)
io.fullreset := CONTROLReg.fullreset
}
object AsyncDebugBusFrom { // OutsideClockDomain
def apply(from_clock: Clock, from_reset: Bool, source: DebugBusIO, depth: Int = 0, sync: Int = 2)(implicit p: Parameters): DebugBusIO = {
val sink = Wire(new DebugBusIO)
sink.req <> AsyncDecoupledFrom(from_clock, from_reset, source.req)
source.resp <> AsyncDecoupledTo(from_clock, from_reset, sink.resp)
sink
}
}
object AsyncDebugBusTo { // OutsideClockDomain
def apply(to_clock: Clock, to_reset: Bool, source: DebugBusIO, depth: Int = 0, sync: Int = 2)(implicit p: Parameters): DebugBusIO = {
val sink = Wire(new DebugBusIO)
sink.req <> AsyncDecoupledTo(to_clock, to_reset, source.req)
source.resp <> AsyncDecoupledFrom(to_clock, to_reset, sink.resp)
sink
}
}