tilelink2: use consistent in/out ports for TLSimpleFactories
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@ -64,7 +64,7 @@ abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatB
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val node = TLRegisterNode(address, concurrency, beatBytes)
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}
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class TLRegBundle[P](val params: P, val tl_in: Vec[TLBundle]) extends Bundle
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class TLRegBundle[P](val params: P, val in: Vec[TLBundle]) extends Bundle
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class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, factory: TLRegFactory)
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extends TLModule(factory) with HasRegMap
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