RocketChip: rename mem to mem_axi in preparation for new bus type
This commit is contained in:
Wesley W. Terpstra
Andrew Waterman
parent
2086c0d603
commit
d2b505f2d2
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@ -88,7 +88,7 @@ class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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}
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class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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val mem = Vec(nMemChannels, new NastiIO)
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val mem_axi = Vec(nMemChannels, new NastiIO)
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO)
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val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO)
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@ -157,7 +157,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
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io.mmio_axi <> uncore.io.mmio_axi
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io.mmio_ahb <> uncore.io.mmio_ahb
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io.mem <> uncore.io.mem
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io.mem_axi <> uncore.io.mem_axi
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}
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/** Wrapper around everything that isn't a Tile.
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@ -169,7 +169,7 @@ class Uncore(implicit val p: Parameters) extends Module
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with HasTopLevelParameters {
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val io = new Bundle {
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val host = new HostIO(htifW)
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val mem = Vec(nMemChannels, new NastiIO)
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val mem_axi = Vec(nMemChannels, new NastiIO)
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val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val prci = Vec(nTiles, new PRCITileIO).asOutput
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@ -193,7 +193,7 @@ class Uncore(implicit val p: Parameters) extends Module
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buildMMIONetwork(p.alterPartial({case TLId => "MMIO_Outermost"}))
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// Wire the htif to the memory port(s) and host interface
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io.mem <> outmemsys.io.mem
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io.mem_axi <> outmemsys.io.mem_axi
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if(p(UseHtifClockDiv)) {
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VLSIUtils.padOutHTIFWithDividedClock(htif.io.host, scrFile.io.scr, io.host, htifW)
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} else {
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@ -270,7 +270,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val htif_uncached = (new ClientUncachedTileLinkIO).flip
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val incoherent = Vec(nTiles, Bool()).asInput
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val mem = Vec(nMemChannels, new NastiIO)
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val mem_axi = Vec(nMemChannels, new NastiIO)
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val mmio = new ClientUncachedTileLinkIO()(p.alterPartial({case TLId => "L2toMMIO"}))
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}
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@ -325,7 +325,7 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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TileLinkWidthAdapter(unwrap.io.out, icPort)
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}
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for ((nasti, tl) <- io.mem zip mem_ic.io.out) {
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for ((nasti, tl) <- io.mem_axi zip mem_ic.io.out) {
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TopUtils.connectTilelinkNasti(nasti, tl)(outermostTLParams)
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// Memory cache type should be normal non-cacheable bufferable
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// TODO why is this happening here? Would 0000 (device) be OK instead?
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@ -151,55 +151,55 @@ object TestBenchGeneration extends FileSystemUtilities {
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""" } mkString
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val nasti_connections = (0 until nMemChannel) map { i => s"""
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.io_mem_${i}_ar_valid (ar_valid_delay_$i),
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.io_mem_${i}_ar_ready (ar_ready_delay_$i),
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.io_mem_${i}_ar_bits_addr (ar_addr_delay_$i),
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.io_mem_${i}_ar_bits_id (ar_id_delay_$i),
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.io_mem_${i}_ar_bits_size (ar_size_delay_$i),
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.io_mem_${i}_ar_bits_len (ar_len_delay_$i),
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.io_mem_${i}_ar_bits_burst (),
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.io_mem_${i}_ar_bits_lock (),
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.io_mem_${i}_ar_bits_cache (),
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.io_mem_${i}_ar_bits_prot (),
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.io_mem_${i}_ar_bits_qos (),
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.io_mem_${i}_ar_bits_region (),
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.io_mem_${i}_ar_bits_user (),
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.io_mem_axi_${i}_ar_valid (ar_valid_delay_$i),
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.io_mem_axi_${i}_ar_ready (ar_ready_delay_$i),
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.io_mem_axi_${i}_ar_bits_addr (ar_addr_delay_$i),
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.io_mem_axi_${i}_ar_bits_id (ar_id_delay_$i),
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.io_mem_axi_${i}_ar_bits_size (ar_size_delay_$i),
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.io_mem_axi_${i}_ar_bits_len (ar_len_delay_$i),
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.io_mem_axi_${i}_ar_bits_burst (),
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.io_mem_axi_${i}_ar_bits_lock (),
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.io_mem_axi_${i}_ar_bits_cache (),
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.io_mem_axi_${i}_ar_bits_prot (),
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.io_mem_axi_${i}_ar_bits_qos (),
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.io_mem_axi_${i}_ar_bits_region (),
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.io_mem_axi_${i}_ar_bits_user (),
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.io_mem_${i}_aw_valid (aw_valid_delay_$i),
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.io_mem_${i}_aw_ready (aw_ready_delay_$i),
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.io_mem_${i}_aw_bits_addr (aw_addr_delay_$i),
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.io_mem_${i}_aw_bits_id (aw_id_delay_$i),
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.io_mem_${i}_aw_bits_size (aw_size_delay_$i),
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.io_mem_${i}_aw_bits_len (aw_len_delay_$i),
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.io_mem_${i}_aw_bits_burst (),
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.io_mem_${i}_aw_bits_lock (),
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.io_mem_${i}_aw_bits_cache (),
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.io_mem_${i}_aw_bits_prot (),
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.io_mem_${i}_aw_bits_qos (),
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.io_mem_${i}_aw_bits_region (),
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.io_mem_${i}_aw_bits_user (),
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.io_mem_axi_${i}_aw_valid (aw_valid_delay_$i),
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.io_mem_axi_${i}_aw_ready (aw_ready_delay_$i),
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.io_mem_axi_${i}_aw_bits_addr (aw_addr_delay_$i),
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.io_mem_axi_${i}_aw_bits_id (aw_id_delay_$i),
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.io_mem_axi_${i}_aw_bits_size (aw_size_delay_$i),
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.io_mem_axi_${i}_aw_bits_len (aw_len_delay_$i),
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.io_mem_axi_${i}_aw_bits_burst (),
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.io_mem_axi_${i}_aw_bits_lock (),
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.io_mem_axi_${i}_aw_bits_cache (),
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.io_mem_axi_${i}_aw_bits_prot (),
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.io_mem_axi_${i}_aw_bits_qos (),
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.io_mem_axi_${i}_aw_bits_region (),
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.io_mem_axi_${i}_aw_bits_user (),
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.io_mem_${i}_w_valid (w_valid_delay_$i),
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.io_mem_${i}_w_ready (w_ready_delay_$i),
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.io_mem_${i}_w_bits_id (),
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.io_mem_${i}_w_bits_strb (w_strb_delay_$i),
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.io_mem_${i}_w_bits_data (w_data_delay_$i),
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.io_mem_${i}_w_bits_last (w_last_delay_$i),
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.io_mem_${i}_w_bits_user (),
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.io_mem_axi_${i}_w_valid (w_valid_delay_$i),
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.io_mem_axi_${i}_w_ready (w_ready_delay_$i),
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.io_mem_axi_${i}_w_bits_id (),
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.io_mem_axi_${i}_w_bits_strb (w_strb_delay_$i),
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.io_mem_axi_${i}_w_bits_data (w_data_delay_$i),
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.io_mem_axi_${i}_w_bits_last (w_last_delay_$i),
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.io_mem_axi_${i}_w_bits_user (),
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.io_mem_${i}_r_valid (r_valid_delay_$i),
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.io_mem_${i}_r_ready (r_ready_delay_$i),
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.io_mem_${i}_r_bits_resp (r_resp_delay_$i),
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.io_mem_${i}_r_bits_id (r_id_delay_$i),
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.io_mem_${i}_r_bits_data (r_data_delay_$i),
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.io_mem_${i}_r_bits_last (r_last_delay_$i),
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.io_mem_${i}_r_bits_user (1'b0),
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.io_mem_axi_${i}_r_valid (r_valid_delay_$i),
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.io_mem_axi_${i}_r_ready (r_ready_delay_$i),
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.io_mem_axi_${i}_r_bits_resp (r_resp_delay_$i),
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.io_mem_axi_${i}_r_bits_id (r_id_delay_$i),
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.io_mem_axi_${i}_r_bits_data (r_data_delay_$i),
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.io_mem_axi_${i}_r_bits_last (r_last_delay_$i),
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.io_mem_axi_${i}_r_bits_user (1'b0),
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.io_mem_${i}_b_valid (b_valid_delay_$i),
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.io_mem_${i}_b_ready (b_ready_delay_$i),
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.io_mem_${i}_b_bits_resp (b_resp_delay_$i),
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.io_mem_${i}_b_bits_id (b_id_delay_$i),
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.io_mem_${i}_b_bits_user (1'b0),
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.io_mem_axi_${i}_b_valid (b_valid_delay_$i),
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.io_mem_axi_${i}_b_ready (b_ready_delay_$i),
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.io_mem_axi_${i}_b_bits_resp (b_resp_delay_$i),
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.io_mem_axi_${i}_b_bits_id (b_id_delay_$i),
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.io_mem_axi_${i}_b_bits_user (1'b0),
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""" } mkString
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@ -323,37 +323,37 @@ object TestBenchGeneration extends FileSystemUtilities {
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val nMemChannel = p(NMemoryChannels)
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val assigns = (0 until nMemChannel).map { i => s"""
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mem_ar_valid[$i] = &tile.Top__io_mem_${i}_ar_valid;
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mem_ar_ready[$i] = &tile.Top__io_mem_${i}_ar_ready;
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mem_ar_bits_addr[$i] = &tile.Top__io_mem_${i}_ar_bits_addr;
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mem_ar_bits_id[$i] = &tile.Top__io_mem_${i}_ar_bits_id;
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mem_ar_bits_size[$i] = &tile.Top__io_mem_${i}_ar_bits_size;
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mem_ar_bits_len[$i] = &tile.Top__io_mem_${i}_ar_bits_len;
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mem_ar_valid[$i] = &tile.Top__io_mem_axi_${i}_ar_valid;
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mem_ar_ready[$i] = &tile.Top__io_mem_axi_${i}_ar_ready;
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mem_ar_bits_addr[$i] = &tile.Top__io_mem_axi_${i}_ar_bits_addr;
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mem_ar_bits_id[$i] = &tile.Top__io_mem_axi_${i}_ar_bits_id;
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mem_ar_bits_size[$i] = &tile.Top__io_mem_axi_${i}_ar_bits_size;
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mem_ar_bits_len[$i] = &tile.Top__io_mem_axi_${i}_ar_bits_len;
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mem_aw_valid[$i] = &tile.Top__io_mem_${i}_aw_valid;
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mem_aw_ready[$i] = &tile.Top__io_mem_${i}_aw_ready;
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mem_aw_bits_addr[$i] = &tile.Top__io_mem_${i}_aw_bits_addr;
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mem_aw_bits_id[$i] = &tile.Top__io_mem_${i}_aw_bits_id;
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mem_aw_bits_size[$i] = &tile.Top__io_mem_${i}_aw_bits_size;
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mem_aw_bits_len[$i] = &tile.Top__io_mem_${i}_aw_bits_len;
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mem_aw_valid[$i] = &tile.Top__io_mem_axi_${i}_aw_valid;
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mem_aw_ready[$i] = &tile.Top__io_mem_axi_${i}_aw_ready;
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mem_aw_bits_addr[$i] = &tile.Top__io_mem_axi_${i}_aw_bits_addr;
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mem_aw_bits_id[$i] = &tile.Top__io_mem_axi_${i}_aw_bits_id;
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mem_aw_bits_size[$i] = &tile.Top__io_mem_axi_${i}_aw_bits_size;
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mem_aw_bits_len[$i] = &tile.Top__io_mem_axi_${i}_aw_bits_len;
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mem_w_valid[$i] = &tile.Top__io_mem_${i}_w_valid;
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mem_w_ready[$i] = &tile.Top__io_mem_${i}_w_ready;
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mem_w_bits_data[$i] = &tile.Top__io_mem_${i}_w_bits_data;
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mem_w_bits_strb[$i] = &tile.Top__io_mem_${i}_w_bits_strb;
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mem_w_bits_last[$i] = &tile.Top__io_mem_${i}_w_bits_last;
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mem_w_valid[$i] = &tile.Top__io_mem_axi_${i}_w_valid;
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mem_w_ready[$i] = &tile.Top__io_mem_axi_${i}_w_ready;
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mem_w_bits_data[$i] = &tile.Top__io_mem_axi_${i}_w_bits_data;
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mem_w_bits_strb[$i] = &tile.Top__io_mem_axi_${i}_w_bits_strb;
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mem_w_bits_last[$i] = &tile.Top__io_mem_axi_${i}_w_bits_last;
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mem_b_valid[$i] = &tile.Top__io_mem_${i}_b_valid;
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mem_b_ready[$i] = &tile.Top__io_mem_${i}_b_ready;
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mem_b_bits_resp[$i] = &tile.Top__io_mem_${i}_b_bits_resp;
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mem_b_bits_id[$i] = &tile.Top__io_mem_${i}_b_bits_id;
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mem_b_valid[$i] = &tile.Top__io_mem_axi_${i}_b_valid;
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mem_b_ready[$i] = &tile.Top__io_mem_axi_${i}_b_ready;
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mem_b_bits_resp[$i] = &tile.Top__io_mem_axi_${i}_b_bits_resp;
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mem_b_bits_id[$i] = &tile.Top__io_mem_axi_${i}_b_bits_id;
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mem_r_valid[$i] = &tile.Top__io_mem_${i}_r_valid;
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mem_r_ready[$i] = &tile.Top__io_mem_${i}_r_ready;
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mem_r_bits_resp[$i] = &tile.Top__io_mem_${i}_r_bits_resp;
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mem_r_bits_id[$i] = &tile.Top__io_mem_${i}_r_bits_id;
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mem_r_bits_data[$i] = &tile.Top__io_mem_${i}_r_bits_data;
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mem_r_bits_last[$i] = &tile.Top__io_mem_${i}_r_bits_last;
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mem_r_valid[$i] = &tile.Top__io_mem_axi_${i}_r_valid;
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mem_r_ready[$i] = &tile.Top__io_mem_axi_${i}_r_ready;
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mem_r_bits_resp[$i] = &tile.Top__io_mem_axi_${i}_r_bits_resp;
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mem_r_bits_id[$i] = &tile.Top__io_mem_axi_${i}_r_bits_id;
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mem_r_bits_data[$i] = &tile.Top__io_mem_axi_${i}_r_bits_data;
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mem_r_bits_last[$i] = &tile.Top__io_mem_axi_${i}_r_bits_last;
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""" }.mkString
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