tilelink2: first cut at parameterization
This commit is contained in:
Wesley W. Terpstra
parent
59a2e6a4dc
commit
7328b55abd
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@ -0,0 +1,41 @@
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import scala.collection.mutable.ListBuffer
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import chisel3.internal.sourceinfo.SourceInfo
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abstract class TLFactory
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{
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private val bindings = ListBuffer[(TLBaseNode, Int, TLBaseNode, Int, SourceInfo)]()
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def tl(manager: TLBaseNode, client: TLBaseNode)(implicit sourceInfo: SourceInfo) = {
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val (i, j) = manager.edge(client)
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bindings += ((manager, i, client, j, sourceInfo))
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}
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def module: TLModule
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protected[tilelink2] def instantiate() = {
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// Find all TLFactory members of self
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for (m <- getClass.getMethods) {
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if (m.getParameterTypes.isEmpty &&
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!java.lang.reflect.Modifier.isStatic(m.getModifiers) &&
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!(m.getName contains '$') &&
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classOf[TLFactory].isAssignableFrom(m.getReturnType)) {
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// ... and force their lazy module members to exist
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m.invoke(this).asInstanceOf[TLFactory].module
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}
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}
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bindings.foreach { case (x, i, y, j, s) =>
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x.bundleIn(i).<>(y.bundleOut(j))(s)
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}
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}
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}
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abstract class TLModule(factory: TLFactory) extends Module
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{
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override def desiredName = factory.getClass.getName.split('.').last
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factory.instantiate()
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}
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@ -0,0 +1,77 @@
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
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{
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override def cloneType = {
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try {
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this.getClass.getConstructors.head.newInstance(params).asInstanceOf[this.type]
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} catch {
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case e: java.lang.IllegalArgumentException =>
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throwException("Unable to use TLBundleBase.cloneType on " +
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this.getClass + ", probably because " + this.getClass +
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"() takes more than one argument. Consider overriding " +
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"cloneType() on " + this.getClass, e)
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}
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}
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}
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class TLBundleA(params: TLBundleParameters) extends TLBundleBase(params)
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{
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val opcode = UInt(width = 3)
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val param = UInt(width = 3) // amo_opcode || perms(req)
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val size = UInt(width = params.sizeBits)
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val source = UInt(width = params.sourceBits) // from
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val address = UInt(width = params.addressBits) // to
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val wmask = UInt(width = params.dataBits/8)
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val data = UInt(width = params.dataBits)
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}
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class TLBundleB(params: TLBundleParameters) extends TLBundleBase(params)
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{
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val opcode = UInt(width = 3)
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val param = UInt(width = 3) // amo_opcode || perms(req)
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val size = UInt(width = params.sizeBits)
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val source = UInt(width = params.sourceBits) // to
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val address = UInt(width = params.addressBits) // from
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val wmask = UInt(width = params.dataBits/8)
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val data = UInt(width = params.dataBits)
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}
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class TLBundleC(params: TLBundleParameters) extends TLBundleBase(params)
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{
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val opcode = UInt(width = 3)
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val param = UInt(width = 3) // perms(from=>to)
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val size = UInt(width = params.sizeBits)
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val address = UInt(width = params.addressBits) // to
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val data = UInt(width = params.dataBits)
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val error = Bool()
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}
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class TLBundleD(params: TLBundleParameters) extends TLBundleBase(params)
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{
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val opcode = UInt(width = 3)
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val param = UInt(width = 3) // perms(to)
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val size = UInt(width = params.sizeBits)
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val source = UInt(width = params.sourceBits) // to
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val sink = UInt(width = params.sinkBits) // from
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val data = UInt(width = params.dataBits)
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val error = Bool()
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}
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class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params)
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{
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val sink = UInt(width = params.sourceBits) // to
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}
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class TLBundle(params: TLBundleParameters) extends TLBundleBase(params)
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{
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val a = Decoupled(new TLBundleA(params))
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val b = Decoupled(new TLBundleB(params)).flip
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val c = Decoupled(new TLBundleC(params))
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val d = Decoupled(new TLBundleD(params)).flip
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val e = Decoupled(new TLBundleE(params))
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}
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@ -0,0 +1,121 @@
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import scala.collection.mutable.ListBuffer
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class TLBaseNode(
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private val clientFn: Option[Seq[TLClientPortParameters] => TLClientPortParameters],
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private val managerFn: Option[Seq[TLManagerPortParameters] => TLManagerPortParameters],
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private val numClientPorts: Range.Inclusive,
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private val numManagerPorts: Range.Inclusive)
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{
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// At least 0 ports must be supported
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require (!numClientPorts.isEmpty)
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require (!numManagerPorts.isEmpty)
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require (numClientPorts.start >= 0)
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require (numManagerPorts.start >= 0)
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val noClients = numClientPorts.size == 1 && numClientPorts.contains(0)
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val noManagers = numManagerPorts.size == 1 && numManagerPorts.contains(0)
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require (noClients || clientFn.isDefined)
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require (noManagers || managerFn.isDefined)
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private val accClientPorts = ListBuffer[TLBaseNode]()
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private val accManagerPorts = ListBuffer[TLBaseNode]()
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private var clientRealized = false
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private var managerRealized = false
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protected[tilelink2] def edge(x: TLBaseNode) = {
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require (!noManagers)
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require (!managerRealized)
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require (!x.noClients)
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require (!x.clientRealized)
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val i = accManagerPorts.size
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val j = x.accClientPorts.size
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accManagerPorts += x
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x.accClientPorts += this
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(i, j)
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}
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private lazy val clientPorts = { clientRealized = true; require (numClientPorts.contains(accClientPorts.size)); accClientPorts.result() }
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private lazy val managerPorts = { managerRealized = true; require (numManagerPorts.contains(accManagerPorts.size)); accManagerPorts.result() }
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private lazy val clientParams : Option[TLClientPortParameters] = clientFn.map(_(managerPorts.map(_.clientParams.get)))
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private lazy val managerParams : Option[TLManagerPortParameters] = managerFn.map(_(clientPorts.map(_.managerParams.get)))
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lazy val edgesOut = clientPorts.map { n => new TLEdgeOut(clientParams.get, n.managerParams.get) }
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lazy val edgesIn = managerPorts.map { n => new TLEdgeIn (n.clientParams.get, managerParams.get) }
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lazy val bundleOut = Vec(edgesOut.size, new TLBundle(edgesOut.map(_.bundle).reduce(_.union(_))))
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lazy val bundleIn = Vec(edgesIn .size, new TLBundle(edgesIn .map(_.bundle).reduce(_.union(_)))).flip
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}
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class TLClientNode(
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params: TLClientParameters,
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numPorts: Range.Inclusive = 1 to 1) extends TLBaseNode(
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clientFn = Some {case Seq() => TLClientPortParameters(Seq(params))},
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managerFn = None,
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numClientPorts = numPorts,
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numManagerPorts = 0 to 0)
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{
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require(numPorts.end >= 1)
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}
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object TLClientNode
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{
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def apply(
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params: TLClientParameters,
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numPorts: Range.Inclusive = 1 to 1) = new TLClientNode(params, numPorts)
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}
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class TLManagerNode(
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beatBytes: Int,
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params: TLManagerParameters,
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numPorts: Range.Inclusive = 1 to 1) extends TLBaseNode(
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clientFn = None,
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managerFn = Some {case Seq() => TLManagerPortParameters(Seq(params), beatBytes)},
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numClientPorts = 0 to 0,
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numManagerPorts = numPorts)
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{
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require(numPorts.end >= 1)
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}
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object TLManagerNode
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{
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def apply(
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beatBytes: Int,
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params: TLManagerParameters,
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numPorts: Range.Inclusive = 1 to 1) = new TLManagerNode(beatBytes, params, numPorts)
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}
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class TLAdapterNode(
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clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
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managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
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numClientPorts: Range.Inclusive = 1 to 1,
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numManagerPorts: Range.Inclusive = 1 to 1) extends TLBaseNode(
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clientFn = Some(clientFn),
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managerFn = Some(managerFn),
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numClientPorts = numClientPorts,
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numManagerPorts = numManagerPorts)
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object TLAdapterNode
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{
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def apply(
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clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
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managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
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numClientPorts: Range.Inclusive = 1 to 1,
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numManagerPorts: Range.Inclusive = 1 to 1) = new TLAdapterNode(clientFn, managerFn, numClientPorts, numManagerPorts)
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}
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class TLIDNode extends TLBaseNode(
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clientFn = Some({case Seq(x) => x}),
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managerFn = Some({case Seq(x) => x}),
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numClientPorts = 1 to 1,
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numManagerPorts = 1 to 1)
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object TLIDNode
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{
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def apply() = new TLIDNode()
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}
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@ -0,0 +1,51 @@
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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class TLEdgeOut(
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client: TLClientPortParameters,
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manager: TLManagerPortParameters)
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extends TLEdgeParameters(client, manager)
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{
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// Transfers
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def Acquire(x: Int) = () // A
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def Release(x: Int) = () // C
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def ReleaseData(x: Int) = () // C
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def ProbeAck(x: Int) = () // C
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def ProbeDataAck(x: Int) = () // C
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def GrantAck(x: Int) = () // E
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// Accessors
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def Get(x: Int) = () // A
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def Put(x: Int) = () // A
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def Atomic(x: Int) = () // A
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def AccessAck(x: Int) = () // C
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def AccessDataAck(x: Int) = () // C
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def Hint(x: Int) = () // A
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def HintAck(x: Int) = () // C
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}
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class TLEdgeIn(
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client: TLClientPortParameters,
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manager: TLManagerPortParameters)
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extends TLEdgeParameters(client, manager)
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{
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// Transfers
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def Probe(x: Int) = () // B
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def Grant(x: Int) = () // D
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def GrantData(x: Int) = () // D
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def ReleaseAck(x: Int) = () // D
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// Accessors
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def Get(x: Int) = () // B
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def Put(x: Int) = () // B
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def Atomic(x: Int) = () // B
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def AccessAck(x: Int) = () // D
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def AccessDataAck(x: Int) = () // D
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def Hint(x: Int) = () // B
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def HintAck(x: Int) = () // D
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}
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@ -0,0 +1,205 @@
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import scala.math.max
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/** Options for memory regions */
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object RegionType {
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sealed trait T
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case object CACHED extends T
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case object TRACKED extends T
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case object UNCACHED extends T
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case object UNCACHEABLE extends T
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val cases = Seq(CACHED, TRACKED, UNCACHED, UNCACHEABLE)
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}
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// A non-empty half-open range; [start, end)
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case class IdRange(start: Int, end: Int)
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{
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require (start >= 0)
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require (end >= 0)
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require (start < end) // not empty
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// This is a strict partial ordering
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def <(x: IdRange) = end <= x.start
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def >(x: IdRange) = x < this
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def overlaps(x: IdRange) = start < x.end && x.start < end
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def contains(x: IdRange) = start <= x.start && x.end <= end
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// contains => overlaps (because empty is forbidden)
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def contains(x: Int) = start <= x && x < end
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def contains(x: UInt) = UInt(start) <= x && x < UInt(end) // !!! special-case =
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def shift(x: Int) = IdRange(start+x, end+x)
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}
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// An potentially empty inclusive range of 2-powers [min, max]
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case class TransferSizes(min: Int, max: Int)
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{
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def this(x: Int) = this(x, x)
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require (min <= max)
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require (min != 0 || max == 0)
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require (max == 0 || isPow2(max))
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require (min == 0 || isPow2(min))
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def none = min == 0
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def contains(x: Int) = isPow2(x) && min <= x && x <= max
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def containsLg(x: Int) = contains(1 << x)
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def containsLg(x: UInt) = if (none) Bool(false) else { UInt(log2Ceil(min)) <= x && x <= UInt(log2Ceil(max)) } // !!! special-case =
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def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
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def intersect(x: TransferSizes) =
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if (x.max < min || min < x.max) TransferSizes.none
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else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
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}
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object TransferSizes {
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def apply(x: Int) = new TransferSizes(x)
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val none = new TransferSizes(0)
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}
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// AddressSets specify the mask of bits consumed by the manager
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// The base address used by the crossbar for routing
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case class AddressSet(mask: BigInt, base: Option[BigInt] = None)
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{
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// Forbid empty sets
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require (base == None || (base.get & mask) == 0)
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def contains(x: BigInt) = ((x ^ base.get) & ~mask) == 0
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def contains(x: UInt) = ((x ^ UInt(base.get)) & UInt(~mask)) === UInt(0)
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// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
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// if base = None, it will be auto-assigned and thus not overlap anything
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def overlaps(x: AddressSet) = (base, x.base) match {
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case (Some(tbase), Some(xbase)) => (~(mask | x.mask) & (tbase ^ xbase)) == 0
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case _ => false
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}
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// contains iff bitwise: x.mask => mask && contains(x.base)
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def contains(x: AddressSet) = ((x.mask | (base.get ^ x.base.get)) & ~mask) == 0
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// 1 less than the number of bytes to which the manager should be aligned
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def alignment1 = ((mask + 1) & ~mask) - 1
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def max = base.get | mask
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}
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case class TLManagerParameters(
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address: Seq[AddressSet],
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sinkId: IdRange = IdRange(0, 1),
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regionType: RegionType.T = RegionType.UNCACHEABLE,
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// Supports both Acquire+Release of these sizes
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supportsAcquire: TransferSizes = TransferSizes.none,
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supportsAtomic: TransferSizes = TransferSizes.none,
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supportsGet: TransferSizes = TransferSizes.none,
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supportsPutFull: TransferSizes = TransferSizes.none,
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supportsPutPartial: TransferSizes = TransferSizes.none,
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supportsHints: Boolean = false,
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// If fifoId=Some, all messages sent to the same fifoId are delivered in FIFO order
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fifoId: Option[Int] = None)
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{
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address.combinations(2).foreach({ case Seq(x,y) =>
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require (!x.overlaps(y))
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})
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address.foreach({ case a =>
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require (supportsAcquire.none || a.alignment1 >= supportsAcquire.max-1)
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})
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val maxTransfer = List(
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supportsAcquire.max,
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supportsAtomic.max,
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supportsGet.max,
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supportsPutFull.max,
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supportsPutPartial.max).max
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}
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case class TLManagerPortParameters(managers: Seq[TLManagerParameters], beatBytes: Int)
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{
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require (isPow2(beatBytes))
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// Require disjoint ranges for Ids and addresses
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managers.combinations(2).foreach({ case Seq(x,y) =>
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require (!x.sinkId.overlaps(y.sinkId))
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x.address.foreach({ a => y.address.foreach({ b =>
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require (!a.overlaps(b))
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})})
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})
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def endSinkId = managers.map(_.sinkId.end).max
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def maxAddress = managers.map(_.address.map(_.max).max).max
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def maxGet = managers.map(_.supportsGet.max).max
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def maxTransfer = managers.map(_.maxTransfer).max
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// These return Option[TLSinkParameters] for your convenience
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def findById(x: Int) = managers.find(_.sinkId.contains(x))
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def findByAddress(x: BigInt) = managers.find(_.address.exists(_.contains(x)))
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//def buildCacheInfo(): UInt => Chilse(RegionType) // UInt = address, not sink_id
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//def buildAtomicInfo(): UInt => Bool
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}
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case class TLClientParameters(
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sourceId: IdRange = IdRange(0,1),
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// Supports both Probe+Grant of these sizes
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supportsProbe: TransferSizes = TransferSizes.none,
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supportsAtomics: TransferSizes = TransferSizes.none,
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supportsGet: TransferSizes = TransferSizes.none,
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supportsPutFull: TransferSizes = TransferSizes.none,
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supportsPutPartial: TransferSizes = TransferSizes.none,
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supportsHints: Boolean = false)
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{
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val maxTransfer = List(
|
||||
supportsProbe.max,
|
||||
supportsAtomics.max,
|
||||
supportsGet.max,
|
||||
supportsPutFull.max,
|
||||
supportsPutPartial.max).max
|
||||
}
|
||||
|
||||
case class TLClientPortParameters(clients: Seq[TLClientParameters]) {
|
||||
def endSourceId = clients.map(_.sourceId.end).max
|
||||
def maxTransfer = clients.map(_.maxTransfer).max
|
||||
// def nSources: Int = sourceView.map(_.sourceIds.count).sum
|
||||
// def nCaches: Int = sourceView.map(s => if(s.supportsProbe) 1 else 0).sum
|
||||
//def makeSourceToCache() = ...
|
||||
//def makeCacheToStartSource() = ...
|
||||
}
|
||||
|
||||
case class TLBundleParameters(
|
||||
addressBits: Int,
|
||||
dataBits: Int,
|
||||
sourceBits: Int,
|
||||
sinkBits: Int,
|
||||
sizeBits: Int)
|
||||
{
|
||||
// Chisel has issues with 0-width wires
|
||||
require (addressBits >= 1)
|
||||
require (dataBits >= 1)
|
||||
require (sourceBits >= 1)
|
||||
require (sinkBits >= 1)
|
||||
require (sizeBits >= 1)
|
||||
require (isPow2(dataBits))
|
||||
|
||||
def union(x: TLBundleParameters) =
|
||||
TLBundleParameters(
|
||||
max(addressBits, x.addressBits),
|
||||
max(dataBits, x.dataBits),
|
||||
max(sourceBits, x.sourceBits),
|
||||
max(sinkBits, x.sinkBits),
|
||||
max(sizeBits, x.sizeBits))
|
||||
}
|
||||
|
||||
case class TLEdgeParameters(
|
||||
client: TLClientPortParameters,
|
||||
manager: TLManagerPortParameters)
|
||||
{
|
||||
val bundle = TLBundleParameters(
|
||||
addressBits = log2Up(manager.maxAddress + 1) - log2Up(manager.beatBytes),
|
||||
dataBits = manager.beatBytes * 8,
|
||||
sourceBits = log2Up(client.endSourceId),
|
||||
sinkBits = log2Up(manager.endSinkId),
|
||||
sizeBits = log2Up(log2Up(max(client.maxTransfer, manager.maxTransfer))+1))
|
||||
}
|
||||
Loading…
Reference in New Issue