tilelink2: rename Factory=>LazyModule and TLModule=>LazyModuleImp
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@ -6,7 +6,7 @@ import Chisel._
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import scala.collection.mutable.ListBuffer
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import chisel3.internal.sourceinfo.SourceInfo
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abstract class TLFactory
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abstract class LazyModule
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{
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private val bindings = ListBuffer[(TLBaseNode, Int, TLBaseNode, Int, SourceInfo)]()
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@ -15,17 +15,17 @@ abstract class TLFactory
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bindings += ((manager, i, client, j, sourceInfo))
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}
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def module: TLModule
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def module: LazyModuleImp
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protected[tilelink2] def instantiate() = {
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// Find all TLFactory members of self
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// Find all LazyModule members of self
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for (m <- getClass.getMethods) {
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if (m.getParameterTypes.isEmpty &&
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!java.lang.reflect.Modifier.isStatic(m.getModifiers) &&
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!(m.getName contains '$') &&
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classOf[TLFactory].isAssignableFrom(m.getReturnType)) {
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classOf[LazyModule].isAssignableFrom(m.getReturnType)) {
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// ... and force their lazy module members to exist
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m.invoke(this).asInstanceOf[TLFactory].module
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m.invoke(this).asInstanceOf[LazyModule].module
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}
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}
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bindings.foreach { case (x, i, y, j, s) =>
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@ -41,14 +41,8 @@ abstract class TLFactory
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}
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}
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// Use this if you have only one node => makes factory adapters possible
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abstract class TLSimpleFactory extends TLFactory
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abstract class LazyModuleImp(outer: LazyModule) extends Module
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{
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def node: TLBaseNode
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}
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abstract class TLModule(factory: TLFactory) extends Module
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{
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override def desiredName = factory.getClass.getName.split('.').last
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factory.instantiate()
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override def desiredName = outer.getClass.getName.split('.').last
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outer.instantiate()
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}
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@ -5,13 +5,13 @@ package uncore.tilelink2
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import Chisel._
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// Acks Hints for managers that don't support them or Acks all Hints if !passthrough
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class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true) extends TLSimpleFactory
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class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true) extends LazyModule
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{
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val node = TLAdapterNode(
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clientFn = { case Seq(c) => if (supportClients) c.copy(clients = c.clients .map(_.copy(supportsHint = true))) else c },
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managerFn = { case Seq(m) => if (supportManagers) m.copy(managers = m.managers.map(_.copy(supportsHint = true))) else m })
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lazy val module = Module(new TLModule(this) {
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lazy val module = Module(new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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@ -7,14 +7,14 @@ import cde.Parameters
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import uncore.tilelink._
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import uncore.constants._
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class TLLegacy(implicit val p: Parameters) extends TLSimpleFactory with HasTileLinkParameters
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class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkParameters
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{
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val outer_p = p
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// TL legacy clients don't support anything fancy
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val node = TLClientNode(TLClientParameters(
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sourceId = IdRange(0, 1 << tlClientXactIdBits)))
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lazy val module = Module(new TLModule(this) with HasTileLinkParameters {
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lazy val module = Module(new LazyModuleImp(this) with HasTileLinkParameters {
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val p = outer_p
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val io = new Bundle {
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val legacy = new ClientUncachedTileLinkIO()(p).flip
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@ -59,25 +59,25 @@ object TLRegisterNode
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// register mapped device from a totally abstract register mapped device.
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// See GPIO.scala in this directory for an example
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abstract class TLRegFactory(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends TLSimpleFactory
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abstract class TLRegisterRouterBase(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends LazyModule
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{
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val node = TLRegisterNode(address, concurrency, beatBytes)
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}
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class TLRegBundle[P](val params: P, val in: Vec[TLBundle]) extends Bundle
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class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, factory: TLRegFactory)
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extends TLModule(factory) with HasRegMap
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class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
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extends LazyModuleImp(router) with HasRegMap
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{
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val io = bundleBuilder
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def regmap(mapping: RegField.Map*) = factory.node.regmap(mapping:_*)
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def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*)
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}
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class TLRegisterRouter[B <: Bundle, M <: TLModule]
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class TLRegisterRouter[B <: Bundle, M <: LazyModuleImp]
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(address: Option[BigInt] = None, size: BigInt = 4096, concurrency: Option[Int] = None, beatBytes: Int = 4)
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(bundleBuilder: Vec[TLBundle] => B)
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(moduleBuilder: (=> B, TLRegFactory) => M)
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extends TLRegFactory(AddressSet(size-1, address), concurrency, beatBytes)
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(moduleBuilder: (=> B, TLRegisterRouterBase) => M)
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extends TLRegisterRouterBase(AddressSet(size-1, address), concurrency, beatBytes)
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{
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require (size % 4096 == 0) // devices should be 4K aligned
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require (isPow2(size))
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@ -4,7 +4,7 @@ package uncore.tilelink2
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import Chisel._
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class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLSimpleFactory
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class TLRAM(address: AddressSet, beatBytes: Int = 4) extends LazyModule
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{
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val node = TLManagerNode(beatBytes, TLManagerParameters(
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address = List(address),
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@ -17,7 +17,7 @@ class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLSimpleFactory
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// We require the address range to include an entire beat (for the write mask)
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require ((address.mask & (beatBytes-1)) == beatBytes-1)
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lazy val module = Module(new TLModule(this) {
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lazy val module = Module(new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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}
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@ -13,7 +13,7 @@ object TLXbar
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}
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}
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class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends TLSimpleFactory
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class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends LazyModule
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{
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def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId))
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def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))
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@ -65,7 +65,7 @@ class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extend
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TLManagerPortParameters(managers, seq(0).beatBytes)
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})
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lazy val module = Module(new TLModule(this) {
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lazy val module = Module(new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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