comparator: a new TileLink stress-tester
This commit is contained in:
Wesley W. Terpstra
Howard Mao
parent
40b6e44816
commit
5562241a50
307
groundtest/src/main/scala/comparator.scala
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307
groundtest/src/main/scala/comparator.scala
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package groundtest
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import Chisel._
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import uncore._
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import junctions._
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import rocket._
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import scala.util.Random
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import cde.{Parameters, Field}
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case class ComparatorParameters(
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targets: Seq[Long],
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width: Int,
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operations: Int,
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atomics: Boolean)
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case object ComparatorKey extends Field[ComparatorParameters]
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trait HasComparatorParameters {
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implicit val p: Parameters
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val comparatorParams = p(ComparatorKey)
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val targets = comparatorParams.targets
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val nTargets = targets.size
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val targetWidth = comparatorParams.width
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val nOperations = comparatorParams.operations
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val atomics = comparatorParams.atomics
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}
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object LFSR64
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{
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private var counter = 0
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private def next: Int = {
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counter += 1
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counter
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}
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def apply(increment: Bool = Bool(true), seed: Int = next): UInt =
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{
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val wide = 64
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val lfsr = RegInit(UInt((seed * 0xDEADBEEFCAFEBAB1L) >>> 1, width = wide))
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val xor = lfsr(0) ^ lfsr(1) ^ lfsr(3) ^ lfsr(4)
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when (increment) { lfsr := Cat(xor, lfsr(wide-1,1)) }
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lfsr
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}
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}
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object NoiseMaker
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{
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def apply(wide: Int, increment: Bool = Bool(true)): UInt = {
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val output = Wire(Vec((wide+63)/64, UInt()))
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output.zipWithIndex.foreach { case (v,i) => v := LFSR64() }
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output.toBits()(wide-1, 0)
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}
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}
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object MaskMaker
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{
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def apply(wide: Int, bits: UInt): UInt =
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Vec.tabulate(wide) {UInt(_) < bits} .toBits() .asUInt()
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}
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class ComparatorSource(implicit val p: Parameters) extends Module
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with HasComparatorParameters
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with HasTileLinkParameters
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{
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val io = new Bundle {
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val out = Valid(new Acquire)
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val finished = Bool(OUTPUT)
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}
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// Output exactly nOperations of Acquires
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val counter = RegInit(UInt(nOperations))
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val finished = RegInit(Bool(false))
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val valid = RegInit(Bool(false))
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valid := Bool(true)
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counter := counter - (!finished && valid).asUInt
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when (counter === UInt(1)) { finished := Bool(true) }
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io.finished := finished
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io.out.valid := !finished && valid
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// Generate random operand sizes
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val raw_operand_size = NoiseMaker(2) | UInt(0, M_SZ)
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val max_operand_size = UInt(log2Up(tlDataBytes))
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val get_operand_size = Mux(raw_operand_size > max_operand_size, max_operand_size, raw_operand_size)
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val atomic_operand_size = Mux(NoiseMaker(1)(0), MT_W, MT_D)
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// Generate random, but valid addr_bytes
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val raw_addr_byte = NoiseMaker(tlByteAddrBits)
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val get_addr_byte = raw_addr_byte & ~MaskMaker(tlByteAddrBits, get_operand_size)
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val atomic_addr_byte = raw_addr_byte & ~MaskMaker(tlByteAddrBits, atomic_operand_size)
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// Only allow some of the possible choices (M_XA_MAXU untested)
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val atomic_opcode = MuxLookup(NoiseMaker(3), M_XA_SWAP, Array(
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UInt("b000") -> M_XA_ADD,
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UInt("b001") -> M_XA_XOR,
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UInt("b010") -> M_XA_OR,
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UInt("b011") -> M_XA_AND,
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UInt("b100") -> M_XA_MIN,
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UInt("b101") -> M_XA_MAX,
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UInt("b110") -> M_XA_MINU,
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UInt("b111") -> M_XA_SWAP))
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// Addr_block range
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val addr_block_mask = MaskMaker(tlBlockAddrBits, UInt(targetWidth-tlBeatAddrBits-tlByteAddrBits))
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// Generate some random values
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val addr_block = NoiseMaker(tlBlockAddrBits) & addr_block_mask
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val addr_beat = NoiseMaker(tlBeatAddrBits)
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val wmask = NoiseMaker(tlDataBytes)
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val data = NoiseMaker(tlDataBits)
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val client_xact_id = UInt(0) // filled by Client
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// Random transactions
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val get = Get(client_xact_id, addr_block, addr_beat, get_addr_byte, get_operand_size, Bool(false))
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val getBlock = GetBlock(client_xact_id, addr_block)
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val put = Put(client_xact_id, addr_block, addr_beat, data, wmask)
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val putBlock = PutBlock(client_xact_id, addr_block, UInt(0), data, SInt(-1, tlDataBytes).asUInt)
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val putAtomic = PutAtomic(client_xact_id, addr_block, addr_beat, atomic_addr_byte, atomic_opcode, atomic_operand_size, data)
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val putPrefetch = PutPrefetch(client_xact_id, addr_block)
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val getPrefetch = GetPrefetch(client_xact_id, addr_block)
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val optAtomic = if (atomics) putAtomic else put
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// Generate a random a_type
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io.out.bits := (new Acquire).fromBits(MuxLookup(NoiseMaker(3), get.toBits, Array(
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UInt("b000") -> get.toBits,
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UInt("b001") -> getBlock.toBits,
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UInt("b010") -> put.toBits,
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UInt("b011") -> putBlock.toBits,
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UInt("b100") -> optAtomic.toBits,
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UInt("b101") -> getPrefetch.toBits,
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UInt("b110") -> putPrefetch.toBits)))
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// We must initially putBlock all of memory to have a consistent starting state
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val final_addr_block = addr_block_mask + UInt(1)
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val wipe_addr_block = RegInit(UInt(0, width = tlBlockAddrBits))
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val done_wipe = wipe_addr_block === final_addr_block
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// Override whatever else we were going to do if we are wiping
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when (!done_wipe) {
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io.out.bits := PutBlock(client_xact_id, wipe_addr_block, UInt(0), data, SInt(-1, tlDataBytes).asUInt)
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when (valid) {
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wipe_addr_block := wipe_addr_block + UInt(1)
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}
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}
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}
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class ComparatorClient(val target: Long)(implicit val p: Parameters) extends Module
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with HasComparatorParameters
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with HasTileLinkParameters
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{
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val io = new Bundle {
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val in = Decoupled(new Acquire).flip
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val tl = new ClientUncachedTileLinkIO()
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val out = Decoupled(new Grant)
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val finished = Bool(OUTPUT)
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}
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val xacts = tlMaxClientXacts
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val offset = (UInt(target) >> UInt(tlBeatAddrBits+tlByteAddrBits))
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// Track the status of inflight requests
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val issued = RegInit(Vec.fill(xacts) {Bool(false)})
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val ready = RegInit(Vec.fill(xacts) {Bool(false)})
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val result = Reg(Vec(xacts, new Grant))
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// Big enough to never stall the broadcast Source
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// (test code not synthesized => big SRAMs are OK)
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val buffer = Queue(io.in, nOperations)
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val queue = Module(new Queue(io.tl.acquire.bits.client_xact_id, xacts))
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val isMultiOut = buffer.bits.hasMultibeatData()
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val isMultiIn = io.tl.grant.bits.hasMultibeatData()
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val beatOut = RegInit(UInt(0, width = tlBeatAddrBits))
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val lastBeat = UInt(tlDataBeats-1)
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val isFirstBeatOut= Mux(isMultiOut, beatOut === UInt(0), Bool(true))
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val isLastBeatOut = Mux(isMultiOut, beatOut === lastBeat, Bool(true))
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val isLastBeatIn = Mux(isMultiIn, io.tl.grant.bits.addr_beat === lastBeat, Bool(true))
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// Remove this once HoldUnless is in chisel3
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def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
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// Potentially issue a request, using a free xact id
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// NOTE: we may retract valid and change xact_id on a !ready (allowed by spec)
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val allow_acq = NoiseMaker(1)(0) && issued.map(!_).reduce(_ || _)
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val xact_id = holdUnless(PriorityEncoder(issued.map(!_)), isFirstBeatOut)
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buffer.ready := allow_acq && io.tl.acquire.ready && isLastBeatOut
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io.tl.acquire.valid := allow_acq && buffer.valid
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io.tl.acquire.bits := buffer.bits
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io.tl.acquire.bits.addr_block := buffer.bits.addr_block + offset
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io.tl.acquire.bits.client_xact_id := xact_id
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when (isMultiOut) {
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io.tl.acquire.bits.addr_beat := beatOut
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io.tl.acquire.bits.data := buffer.bits.data * (beatOut + UInt(1)) // mix the data up a bit
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}
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when (io.tl.acquire.fire()) {
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issued(xact_id) := isLastBeatOut
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when (isMultiOut) { beatOut := beatOut + UInt(1) }
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}
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// Remember the xact ID so we can return results in-order
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queue.io.enq.valid := io.tl.acquire.fire() && isLastBeatOut
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queue.io.enq.bits := xact_id
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assert (queue.io.enq.ready || !queue.io.enq.valid) // should be big enough
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// Capture the results from the manager
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io.tl.grant.ready := NoiseMaker(1)(0)
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when (io.tl.grant.fire()) {
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val id = io.tl.grant.bits.client_xact_id
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assert (!ready(id)) // got same xact_id twice?
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ready(id) := isLastBeatIn
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result(id) := io.tl.grant.bits
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}
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// Bad xact_id returned if ready but not issued!
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assert ((ready zip issued) map {case (r,i) => i || !r} reduce (_ && _))
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// When we have the next grant result, send it to the sink
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val next_id = queue.io.deq.bits
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queue.io.deq.ready := io.out.ready && ready(next_id) // TODO: only compares last getBlock
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io.out.valid := queue.io.deq.valid && ready(next_id)
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io.out.bits := result(queue.io.deq.bits)
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when (io.out.fire()) {
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ready(next_id) := Bool(false)
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issued(next_id) := Bool(false)
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}
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io.finished := !buffer.valid && !issued.reduce(_ || _)
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}
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class ComparatorSink(implicit val p: Parameters) extends Module
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with HasComparatorParameters
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with HasTileLinkParameters
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{
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val io = new Bundle {
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val in = Vec(nTargets, Decoupled(new Grant)).flip
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val finished = Bool(OUTPUT)
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}
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// could use a smaller Queue here, but would couple targets flow controls together
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val queues = io.in.map(Queue(_, nOperations))
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io.finished := queues.map(!_.valid).reduce(_ && _)
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val all_valid = queues.map(_.valid).reduce(_ && _)
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queues.foreach(_.ready := all_valid)
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val base = queues(0).bits
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def check(g: Grant) = {
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assert (g.is_builtin_type, "grant not builtin")
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assert (base.g_type === g.g_type, "g_type mismatch")
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assert (base.addr_beat === g.addr_beat || !g.is(Grant.getDataBlockType), "addr_beat mismatch")
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assert (base.data === g.data || !g.hasData(), "data mismatch")
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}
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when (all_valid) {
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queues.map(_.bits).foreach(check)
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}
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}
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class ComparatorCore(implicit val p: Parameters) extends Module
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with HasComparatorParameters
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with HasTileLinkParameters
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{
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val io = new Bundle {
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val uncached = Vec(nTargets, new ClientUncachedTileLinkIO)
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val finished = Bool(OUTPUT)
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}
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val source = Module(new ComparatorSource)
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val sink = Module(new ComparatorSink)
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val clients = targets.zipWithIndex.map { case (target, index) =>
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val client = Module(new ComparatorClient(target))
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assert (client.io.in.ready) // must accept
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client.io.in := source.io.out
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io.uncached(index) <> client.io.tl
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sink.io.in(index) <> client.io.out
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client
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}
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io.finished := source.io.finished && sink.io.finished && clients.map(_.io.finished).reduce(_ && _)
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}
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class ComparatorTile(resetSignal: Bool)(implicit val p: Parameters) extends Tile(resetSignal)(p)
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with HasComparatorParameters
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with HasTileLinkParameters
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{
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// Make sure we are configured correctly
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require (nCachedTileLinkPorts == 1)
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require (nUncachedTileLinkPorts == nTargets + 1)
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val core = Module(new ComparatorCore)
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val finisher = Module(new GroundTestFinisher)
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// Connect 0..nTargets-1 to core
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(io.uncached zip core.io.uncached) map { case (u, c) => u <> c }
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io.uncached(nTargets) <> finisher.io.mem
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finisher.io.finished := core.io.finished
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// Work-around cachedClients must be >= 1 issue
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io.cached(0).acquire.valid := Bool(false)
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io.cached(0).grant.ready := Bool(false)
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io.cached(0).finish.valid := Bool(false)
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io.cached(0).probe.ready := io.cached(0).release.ready
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io.cached(0).release.valid := io.cached(0).probe.valid
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io.cached(0).release.bits := ClientMetadata.onReset.makeRelease(io.cached(0).probe.bits)
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}
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