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tilelink2: rename wmask => mask since it also applies to reads

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This commit is contained in:
Wesley W. Terpstra
2016-08-30 15:06:37 -07:00
parent 7347b0c4dd
commit 5f6ca0bd0d
5 changed files with 41 additions and 41 deletions
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14
uncore/src/main/scala/tilelink2/Bundles.scala
View File

@@ -119,7 +119,7 @@ trait HasTLOpcode
trait HasTLData extends HasTLOpcode
{
def data(x: Bogus = Bogus()): UInt
def wmask(x: Bogus = Bogus()): UInt
def mask(x: Bogus = Bogus()): UInt
}
class TLBundleA(params: TLBundleParameters)
@@ -131,7 +131,7 @@ class TLBundleA(params: TLBundleParameters)
val size = UInt(width = params.sizeBits)
val source = UInt(width = params.sourceBits) // from
val address = UInt(width = params.addressBits) // to
val wmask = UInt(width = params.dataBits/8)
val mask = UInt(width = params.dataBits/8)
val data = UInt(width = params.dataBits)
def hasData(x: Bogus = Bogus()) = !opcode(2)
@@ -142,7 +142,7 @@ class TLBundleA(params: TLBundleParameters)
def hasFollowUp(x: Bogus = Bogus()) = Bool(true)
def size(x: Bogus = Bogus()) = size
def data(x: Bogus = Bogus()) = data
def wmask(x: Bogus = Bogus()) = wmask
def mask(x: Bogus = Bogus()) = mask
}
class TLBundleB(params: TLBundleParameters)
@@ -154,14 +154,14 @@ class TLBundleB(params: TLBundleParameters)
val size = UInt(width = params.sizeBits)
val source = UInt(width = params.sourceBits) // to
val address = UInt(width = params.addressBits) // from
val wmask = UInt(width = params.dataBits/8)
val mask = UInt(width = params.dataBits/8)
val data = UInt(width = params.dataBits)
def hasData(x: Bogus = Bogus()) = !opcode(2)
def hasFollowUp(x: Bogus = Bogus()) = Bool(true)
def size(x: Bogus = Bogus()) = size
def data(x: Bogus = Bogus()) = data
def wmask(x: Bogus = Bogus()) = wmask
def mask(x: Bogus = Bogus()) = mask
}
class TLBundleC(params: TLBundleParameters)
@@ -185,7 +185,7 @@ class TLBundleC(params: TLBundleParameters)
// opcode === TLMessages.ReleaseData
def size(x: Bogus = Bogus()) = size
def data(x: Bogus = Bogus()) = data
def wmask(x: Bogus = Bogus()) = SInt(-1, width = params.dataBits/8).asUInt
def mask(x: Bogus = Bogus()) = SInt(-1, width = params.dataBits/8).asUInt
}
class TLBundleD(params: TLBundleParameters)
@@ -208,7 +208,7 @@ class TLBundleD(params: TLBundleParameters)
// opcode === TLMessages.GrantData
def size(x: Bogus = Bogus()) = size
def data(x: Bogus = Bogus()) = data
def wmask(x: Bogus = Bogus()) = SInt(-1, width = params.dataBits/8).asUInt
def mask(x: Bogus = Bogus()) = SInt(-1, width = params.dataBits/8).asUInt
}
class TLBundleE(params: TLBundleParameters)

32
uncore/src/main/scala/tilelink2/Monitor.scala
View File

@@ -13,7 +13,7 @@ object TLMonitor
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val wmask = edge.fullMask(bundle.address, bundle.size)
val mask = edge.fullMask(bundle.address, bundle.size)
when (bundle.opcode === TLMessages.Acquire) {
assert (edge.manager.supportsAcquire(bundle.address, bundle.size), "'A' channel carries Acquire type unsupported by manager")(sourceInfo)
@@ -21,7 +21,7 @@ object TLMonitor
assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'A' channel Acquire smaller than a beat")(sourceInfo)
assert (is_aligned, "'A' channel Acquire address not aligned to size")(sourceInfo)
assert (TLPermissions.isGrow(bundle.param), "'A' channel Acquire carries invalid grow param")(sourceInfo)
assert (bundle.wmask === SInt(-1).asUInt, "'A' channel Acquire contains invalid wmask")(sourceInfo)
assert (bundle.mask === SInt(-1).asUInt, "'A' channel Acquire contains invalid mask")(sourceInfo)
}
when (bundle.opcode === TLMessages.Get) {
@@ -29,7 +29,7 @@ object TLMonitor
assert (source_ok, "'A' channel Get carries invalid source ID")(sourceInfo)
assert (is_aligned, "'A' channel Get address not aligned to size")(sourceInfo)
assert (bundle.param === UInt(0), "'A' channel Get carries invalid param")(sourceInfo)
assert (bundle.wmask === wmask, "'A' channel Get contains invalid wmask")(sourceInfo)
assert (bundle.mask === mask, "'A' channel Get contains invalid mask")(sourceInfo)
}
when (bundle.opcode === TLMessages.PutFullData) {
@@ -37,7 +37,7 @@ object TLMonitor
assert (source_ok, "'A' channel PutFull carries invalid source ID")(sourceInfo)
assert (is_aligned, "'A' channel PutFull address not aligned to size")(sourceInfo)
assert (bundle.param === UInt(0), "'A' channel PutFull carries invalid param")(sourceInfo)
assert (bundle.wmask === wmask, "'A' channel PutFull contains invalid wmask")(sourceInfo)
assert (bundle.mask === mask, "'A' channel PutFull contains invalid mask")(sourceInfo)
}
when (bundle.opcode === TLMessages.PutPartialData) {
@@ -45,7 +45,7 @@ object TLMonitor
assert (source_ok, "'A' channel PutPartial carries invalid source ID")(sourceInfo)
assert (is_aligned, "'A' channel PutPartial address not aligned to size")(sourceInfo)
assert (bundle.param === UInt(0), "'A' channel PutPartial carries invalid param")(sourceInfo)
assert ((bundle.wmask & ~wmask) === UInt(0), "'A' channel PutPartial contains invalid wmask")(sourceInfo)
assert ((bundle.mask & ~mask) === UInt(0), "'A' channel PutPartial contains invalid mask")(sourceInfo)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
@@ -53,7 +53,7 @@ object TLMonitor
assert (source_ok, "'A' channel Arithmetic carries invalid source ID")(sourceInfo)
assert (is_aligned, "'A' channel Arithmetic address not aligned to size")(sourceInfo)
assert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param")(sourceInfo)
assert (bundle.wmask === wmask, "'A' channel Arithmetic contains invalid wmask")(sourceInfo)
assert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask")(sourceInfo)
}
when (bundle.opcode === TLMessages.LogicalData) {
@@ -61,14 +61,14 @@ object TLMonitor
assert (source_ok, "'A' channel Logical carries invalid source ID")(sourceInfo)
assert (is_aligned, "'A' channel Logical address not aligned to size")(sourceInfo)
assert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param")(sourceInfo)
assert (bundle.wmask === wmask, "'A' channel Logical contains invalid wmask")(sourceInfo)
assert (bundle.mask === mask, "'A' channel Logical contains invalid mask")(sourceInfo)
}
when (bundle.opcode === TLMessages.Hint) {
assert (edge.manager.supportsHint(bundle.address), "'A' channel carries Hint type unsupported by manager")(sourceInfo)
assert (source_ok, "'A' channel Hint carries invalid source ID")(sourceInfo)
assert (is_aligned, "'A' channel Hint address not aligned to size")(sourceInfo)
assert (bundle.wmask === wmask, "'A' channel Hint contains invalid wmask")(sourceInfo)
assert (bundle.mask === mask, "'A' channel Hint contains invalid mask")(sourceInfo)
}
}
@@ -78,7 +78,7 @@ object TLMonitor
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val wmask = edge.fullMask(bundle.address, bundle.size)
val mask = edge.fullMask(bundle.address, bundle.size)
when (bundle.opcode === TLMessages.Probe) {
assert (edge.client.supportsProbe(bundle.source, bundle.size), "'B' channel carries Probe type unsupported by client")(sourceInfo)
@@ -86,7 +86,7 @@ object TLMonitor
assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'B' channel Probe smaller than a beat")(sourceInfo)
assert (is_aligned, "'B' channel Probe address not aligned to size")(sourceInfo)
assert (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param")(sourceInfo)
assert (bundle.wmask === SInt(-1).asUInt, "'B' channel Probe contains invalid wmask")(sourceInfo)
assert (bundle.mask === SInt(-1).asUInt, "'B' channel Probe contains invalid mask")(sourceInfo)
}
when (bundle.opcode === TLMessages.Get) {
@@ -94,7 +94,7 @@ object TLMonitor
assert (address_ok, "'B' channel Get carries unmanaged address")(sourceInfo)
assert (is_aligned, "'B' channel Get address not aligned to size")(sourceInfo)
assert (bundle.param === UInt(0), "'B' channel Get carries invalid param")(sourceInfo)
assert (bundle.wmask === wmask, "'A' channel Get contains invalid wmask")(sourceInfo)
assert (bundle.mask === mask, "'A' channel Get contains invalid mask")(sourceInfo)
}
when (bundle.opcode === TLMessages.PutFullData) {
@@ -102,7 +102,7 @@ object TLMonitor
assert (address_ok, "'B' channel PutFull carries unmanaged address")(sourceInfo)
assert (is_aligned, "'B' channel PutFull address not aligned to size")(sourceInfo)
assert (bundle.param === UInt(0), "'B' channel PutFull carries invalid param")(sourceInfo)
assert (bundle.wmask === wmask, "'B' channel PutFull contains invalid wmask")(sourceInfo)
assert (bundle.mask === mask, "'B' channel PutFull contains invalid mask")(sourceInfo)
}
when (bundle.opcode === TLMessages.PutPartialData) {
@@ -110,7 +110,7 @@ object TLMonitor
assert (address_ok, "'B' channel PutPartial carries unmanaged address")(sourceInfo)
assert (is_aligned, "'B' channel PutPartial address not aligned to size")(sourceInfo)
assert (bundle.param === UInt(0), "'B' channel PutPartial carries invalid param")(sourceInfo)
assert ((bundle.wmask & ~wmask) === UInt(0), "'B' channel PutPartial contains invalid wmask")(sourceInfo)
assert ((bundle.mask & ~mask) === UInt(0), "'B' channel PutPartial contains invalid mask")(sourceInfo)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
@@ -118,7 +118,7 @@ object TLMonitor
assert (address_ok, "'B' channel Arithmetic carries unmanaged address")(sourceInfo)
assert (is_aligned, "'B' channel Arithmetic address not aligned to size")(sourceInfo)
assert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param")(sourceInfo)
assert (bundle.wmask === wmask, "'B' channel Arithmetic contains invalid wmask")(sourceInfo)
assert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask")(sourceInfo)
}
when (bundle.opcode === TLMessages.LogicalData) {
@@ -126,14 +126,14 @@ object TLMonitor
assert (address_ok, "'B' channel Logical carries unmanaged address")(sourceInfo)
assert (is_aligned, "'B' channel Logical address not aligned to size")(sourceInfo)
assert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param")(sourceInfo)
assert (bundle.wmask === wmask, "'B' channel Logical contains invalid wmask")(sourceInfo)
assert (bundle.mask === mask, "'B' channel Logical contains invalid mask")(sourceInfo)
}
when (bundle.opcode === TLMessages.Hint) {
assert (edge.client.supportsHint(bundle.source), "'B' channel carries Hint type unsupported by client")(sourceInfo)
assert (address_ok, "'B' channel Hint carries unmanaged address")(sourceInfo)
assert (is_aligned, "'B' channel Hint address not aligned to size")(sourceInfo)
assert (bundle.wmask === wmask, "'B' channel Hint contains invalid wmask")(sourceInfo)
assert (bundle.mask === mask, "'B' channel Hint contains invalid mask")(sourceInfo)
}
}

32
uncore/src/main/scala/tilelink2/Operations.scala
View File

@@ -62,7 +62,7 @@ class TLEdgeOut(
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.wmask := SInt(-1).asUInt
a.mask := SInt(-1).asUInt
a.data := UInt(0)
(legal, a)
}
@@ -135,7 +135,7 @@ class TLEdgeOut(
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.wmask := fullMask(toAddress, lgSize)
a.mask := fullMask(toAddress, lgSize)
a.data := UInt(0)
(legal, a)
}
@@ -149,12 +149,12 @@ class TLEdgeOut(
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.wmask := fullMask(toAddress, lgSize)
a.mask := fullMask(toAddress, lgSize)
a.data := data
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, wmask: UInt) = {
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask : UInt) = {
require (manager.anySupportPutPartial)
val legal = manager.supportsPutPartial(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
@@ -163,7 +163,7 @@ class TLEdgeOut(
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.wmask := wmask
a.mask := mask
a.data := data
(legal, a)
}
@@ -177,7 +177,7 @@ class TLEdgeOut(
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.wmask := fullMask(toAddress, lgSize)
a.mask := fullMask(toAddress, lgSize)
a.data := data
(legal, a)
}
@@ -191,7 +191,7 @@ class TLEdgeOut(
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.wmask := fullMask(toAddress, lgSize)
a.mask := fullMask(toAddress, lgSize)
a.data := data
(legal, a)
}
@@ -205,7 +205,7 @@ class TLEdgeOut(
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.wmask := fullMask(toAddress, lgSize)
a.mask := fullMask(toAddress, lgSize)
a.data := UInt(0)
(legal, a)
}
@@ -264,7 +264,7 @@ class TLEdgeIn(
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.wmask := SInt(-1).asUInt
b.mask := SInt(-1).asUInt
b.data := UInt(0)
(legal, b)
}
@@ -317,7 +317,7 @@ class TLEdgeIn(
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.wmask := fullMask(fromAddress, lgSize)
b.mask := fullMask(fromAddress, lgSize)
b.data := UInt(0)
(legal, b)
}
@@ -331,12 +331,12 @@ class TLEdgeIn(
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.wmask := fullMask(fromAddress, lgSize)
b.mask := fullMask(fromAddress, lgSize)
b.data := data
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, wmask: UInt) = {
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask : UInt) = {
require (client.anySupportPutPartial)
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
@@ -345,7 +345,7 @@ class TLEdgeIn(
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.wmask := wmask
b.mask := mask
b.data := data
(legal, b)
}
@@ -359,7 +359,7 @@ class TLEdgeIn(
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.wmask := fullMask(fromAddress, lgSize)
b.mask := fullMask(fromAddress, lgSize)
b.data := data
(legal, b)
}
@@ -373,7 +373,7 @@ class TLEdgeIn(
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.wmask := fullMask(fromAddress, lgSize)
b.mask := fullMask(fromAddress, lgSize)
b.data := data
(legal, b)
}
@@ -387,7 +387,7 @@ class TLEdgeIn(
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.wmask := fullMask(fromAddress, lgSize)
b.mask := fullMask(fromAddress, lgSize)
b.data := UInt(0)
(legal, b)
}

2
uncore/src/main/scala/tilelink2/RegisterRouter.scala
View File

@@ -26,7 +26,7 @@ class TLRegisterNode(address: AddressSet, concurrency: Option[Int] = None, beatB
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := a.bits.address >> log2Ceil(beatBytes)
in.bits.data := a.bits.data
in.bits.mask := a.bits.wmask
in.bits.mask := a.bits.mask
in.bits.extra := Cat(a.bits.source, a.bits.size)
// Invoke the register map builder

2
uncore/src/main/scala/tilelink2/SRAM.scala
View File

@@ -59,7 +59,7 @@ class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLSimpleFactory
when (read) {
rdata := mem.read(memAddress)
} .otherwise {
mem.write(memAddress, wdata, in.a.bits.wmask.toBools)
mem.write(memAddress, wdata, in.a.bits.mask.toBools)
}
}
})