ahb: fix bugs found using comparatortest
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93c1b17b52
commit
7014eef339
@ -140,9 +140,10 @@ class AHBTileLinkIn(supportAtomics: Boolean = false)(implicit val p: Parameters)
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// Calculate the address, with consideration to put fragments and bursts
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val addr_block = io.acquire.bits.addr_block
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val addr_beat = io.acquire.bits.addr_beat
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val addr_burst = Mux(isReadBurst, addr_beat + burst, addr_beat)
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val addr_beatin= io.acquire.bits.addr_beat
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val addr_burst = Mux(isReadBurst, addr_beatin + burst, addr_beatin)
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val addr_byte = Mux(isPut, put_addr, io.acquire.bits.addr_byte())
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val addr_beat = Mux(isWriteBurst, UInt(0), addr_burst)
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val ahbAddr = Cat(addr_block, addr_burst, addr_byte)
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val ahbSize = Mux(isPut, put_size, Mux(isBurst, UInt(log2Ceil(tlDataBytes)), io.acquire.bits.op_size()))
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@ -185,7 +186,7 @@ class AHBTileLinkIn(supportAtomics: Boolean = false)(implicit val p: Parameters)
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Acquire.getType -> Bool(true),
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Acquire.getBlockType -> Bool(true),
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Acquire.putType -> last_wmask,
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Acquire.putBlockType -> Bool(true),
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Acquire.putBlockType -> last_burst,
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Acquire.putAtomicType -> MuxLookup(atom_state, Bool(false), Array(
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s_atom_r -> Bool(true), // they want the old data
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s_atom_idle1 -> Bool(false),
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@ -212,11 +213,13 @@ class AHBTileLinkIn(supportAtomics: Boolean = false)(implicit val p: Parameters)
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io.request.bits.is_builtin_type := Bool(true)
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io.request.bits.g_type := io.acquire.bits.getBuiltInGrantType()
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io.request.bits.client_xact_id := io.acquire.bits.client_xact_id
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io.request.bits.addr_beat := addr_burst
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io.request.bits.addr_beat := addr_beat
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val debugBurst = Reg(UInt())
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debugBurst := addr_burst - burst
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when (io.request.valid) {
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debugBurst := addr_burst - burst
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}
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// We only support built-in TileLink requests
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assert(!io.acquire.valid || io.acquire.bits.is_builtin_type, "AHB bridge only supports builtin TileLink types")
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// Ensure alignment of address to size
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@ -336,7 +339,7 @@ class AHBBusMaster(supportAtomics: Boolean = false)(implicit val p: Parameters)
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case CacheBlockOffsetBits => hastiAddrBits
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case AmoAluOperandBits => hastiDataBits
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})
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val alu = Module(new AMOALU(rhsIsAligned = false)(amo_p))
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val alu = Module(new AMOALU(rhsIsAligned = true)(amo_p))
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alu.io.addr := haddr
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alu.io.cmd := cmd
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alu.io.typ := hsize
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