tilelink2: prototype crossbar implementation
This commit is contained in:
Wesley W. Terpstra
parent
34f65938b6
commit
e506309998
@ -43,7 +43,7 @@ class TLEdge(
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val cutoff = log2Ceil(manager.beatBytes)
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val small = size <= UInt(cutoff)
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val decode = Vec.tabulate (1+maxLgSize-cutoff) { i => UInt(i + cutoff) === size }
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Mux(!hasData || small, UInt(1), decode)
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Mux(!hasData || small, UInt(1), decode.toBits.asUInt)
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}
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}
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@ -19,7 +19,6 @@ object RegionType {
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case class IdRange(start: Int, end: Int)
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{
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require (start >= 0)
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require (end >= 0)
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require (start < end) // not empty
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// This is a strict partial ordering
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@ -38,6 +37,7 @@ case class IdRange(start: Int, end: Int)
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else { UInt(start) <= x && x < UInt(end) }
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def shift(x: Int) = IdRange(start+x, end+x)
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def size = end - start
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}
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// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
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211
uncore/src/main/scala/tilelink2/Xbar.scala
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211
uncore/src/main/scala/tilelink2/Xbar.scala
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@ -0,0 +1,211 @@
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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object TLXbar
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{
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def lowestIndex(requests: Vec[Bool], execute: Bool) = {
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// lowest-index first is stateless; ignore execute
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val ors = Vec(requests.scanLeft(Bool(false))(_ || _).init) // prefix-OR
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Vec((ors zip requests) map { case (o, r) => !o && r })
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}
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}
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class TLXbar(policy: (Vec[Bool], Bool) => Seq[Bool] = TLXbar.lowestIndex) extends TLFactory
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{
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def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId))
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def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))
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def assignRanges(sizes: Seq[Int]) = {
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val pow2Sizes = sizes.map(1 << log2Ceil(_))
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val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
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val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
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val ranges = (tuples zip starts) map { case ((sz, i), st) => (IdRange(st, st+sz), i) }
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ranges.sortBy(_._2).map(_._1) // Restore orignal order
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}
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def relabeler() = {
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var idFactory = 0
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() => {
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val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
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(x: Int) => {
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if (fifoMap.contains(x)) fifoMap(x) else {
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val out = idFactory
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idFactory = idFactory + 1
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fifoMap += (x -> out)
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out
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}
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}
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}
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}
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val node = TLAdapterNode(
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numClientPorts = 1 to 32,
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numManagerPorts = 1 to 32,
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clientFn = { seq =>
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val clients = (mapInputIds(seq) zip seq) flatMap { case (range, port) =>
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port.clients map { client => client.copy(
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sourceId = client.sourceId.shift(range.start)
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)}
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}
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TLClientPortParameters(clients)
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},
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managerFn = { seq =>
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val fifoIdFactory = relabeler()
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val managers = (mapOutputIds(seq) zip seq) flatMap { case (range, port) =>
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require (port.beatBytes == seq(0).beatBytes)
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val fifoIdMapper = fifoIdFactory()
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port.managers map { manager => manager.copy(
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sinkId = manager.sinkId.shift(range.start),
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fifoId = manager.fifoId.map(fifoIdMapper(_))
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)}
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}
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TLManagerPortParameters(managers, seq(0).beatBytes)
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})
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lazy val module = Module(new TLModule(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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// Grab the port ID mapping
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val inputIdRanges = mapInputIds(node.edgesIn.map(_.client))
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val outputIdRanges = mapOutputIds(node.edgesOut.map(_.manager))
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// We need an intermediate size of bundle with the widest possible identifiers
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val wide_bundle = io.in(0).params.union(io.out(0).params)
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// Handle size = 1 gracefully (Chisel3 empty range is broken)
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def trim(id: UInt, size: Int) = if (size <= 1) UInt(0) else id(log2Ceil(size)-1, 0)
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def transpose(x: Seq[Seq[Bool]]) = Vec.tabulate(x(0).size) { i => Vec.tabulate(x.size) { j => x(j)(i) } }
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// Transform input bundle sources (sinks use global namespace on both sides)
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val in = Wire(Vec(io.in.size, TLBundle(wide_bundle)))
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for (i <- 0 until in.size) {
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val r = inputIdRanges(i)
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in(i) <> io.in(i)
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// prefix sources
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in(i).a.bits.source := io.in(i).a.bits.source | UInt(r.start)
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in(i).c.bits.source := io.in(i).c.bits.source | UInt(r.start)
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// defix sources
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io.in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
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io.in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
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}
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// Transform output bundle sinks (sources use global namespace on both sides)
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val out = Wire(Vec(io.out.size, TLBundle(wide_bundle)))
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for (i <- 0 until out.size) {
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val r = outputIdRanges(i)
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io.out(i) <> out(i)
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// prefix sinks
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out(i).d.bits.sink := io.out(i).d.bits.sink | UInt(r.start)
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// defix sinks
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io.out(i).e.bits.sink := trim(out(i).e.bits.sink, r.size)
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}
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// The crossbar cross-connection state; defined later
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val grantedAIO = Wire(Vec(in .size, Vec(out.size, Bool())))
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val grantedBOI = Wire(Vec(out.size, Vec( in.size, Bool())))
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val grantedCIO = Wire(Vec(in .size, Vec(out.size, Bool())))
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val grantedDOI = Wire(Vec(out.size, Vec(in .size, Bool())))
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val grantedEIO = Wire(Vec(in .size, Vec(out.size, Bool())))
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val grantedAOI = transpose(grantedAIO)
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val grantedBIO = transpose(grantedBOI)
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val grantedCOI = transpose(grantedCIO)
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val grantedDIO = transpose(grantedDOI)
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val grantedEOI = transpose(grantedEIO)
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// Mux1H passes a single-source through unmasked. That's bad for control.
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def Mux1C(sel: Seq[Bool], ctl: Seq[Bool]) = (sel zip ctl).map{ case (a,b) => a && b }.reduce(_ || _)
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// Mux clients to managers
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for (o <- 0 until out.size) {
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out(o).a.valid := Mux1C(grantedAOI(o), in.map(_.a.valid))
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out(o).a.bits := Mux1H(grantedAOI(o), in.map(_.a.bits))
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out(o).b.ready := Mux1C(grantedBOI(o), in.map(_.b.ready))
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out(o).c.valid := Mux1C(grantedCOI(o), in.map(_.c.valid))
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out(o).c.bits := Mux1H(grantedCOI(o), in.map(_.c.bits))
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out(o).d.ready := Mux1C(grantedDOI(o), in.map(_.d.ready))
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out(o).e.valid := Mux1C(grantedEOI(o), in.map(_.e.valid))
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out(o).e.bits := Mux1H(grantedEOI(o), in.map(_.e.bits))
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}
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// Mux managers to clients
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for (i <- 0 until in.size) {
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in(i).a.ready := Mux1C(grantedAIO(i), out.map(_.a.ready))
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in(i).b.valid := Mux1C(grantedBIO(i), out.map(_.b.valid))
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in(i).b.bits := Mux1H(grantedBIO(i), out.map(_.b.bits))
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in(i).c.ready := Mux1C(grantedCIO(i), out.map(_.c.ready))
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in(i).d.valid := Mux1C(grantedDIO(i), out.map(_.d.valid))
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in(i).d.bits := Mux1H(grantedDIO(i), out.map(_.d.bits))
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in(i).e.ready := Mux1C(grantedEIO(i), out.map(_.e.ready))
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}
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val requestAIO = Vec(in.map { i => Vec(node.edgesOut.map { o => i.a.valid && o.manager.contains(i.a.bits.address) }) })
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val requestBOI = Vec(out.map { o => Vec(inputIdRanges.map { i => o.b.valid && i .contains(o.b.bits.source) }) })
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val requestCIO = Vec(in.map { i => Vec(node.edgesOut.map { o => i.c.valid && o.manager.contains(i.c.bits.address) }) })
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val requestDOI = Vec(out.map { o => Vec(inputIdRanges.map { i => o.d.valid && i .contains(o.b.bits.source) }) })
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val requestEIO = Vec(in.map { i => Vec(outputIdRanges.map { o => i.e.valid && o .contains(i.e.bits.sink) }) })
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val beatsA = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats(i.a.bits) })
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val beatsB = Vec((out zip node.edgesOut) map { case (o, e) => e.numBeats(o.b.bits) })
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val beatsC = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats(i.c.bits) })
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val beatsD = Vec((out zip node.edgesOut) map { case (o, e) => e.numBeats(o.d.bits) })
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val beatsE = Vec((in zip node.edgesIn) map { case (i, e) => e.numBeats(i.e.bits) })
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// Which pairs support support transfers
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val maskIO = Vec.tabulate(in.size) { i => Vec.tabulate(out.size) { o =>
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Bool(node.edgesIn(i).client.anySupportProbe && node.edgesOut(o).manager.anySupportAcquire)
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} }
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val maskOI = transpose(maskIO)
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// Mask out BCE channel connections (to be optimized away) for transfer-incapable pairings
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def mask(a: Seq[Seq[Bool]], b: Seq[Seq[Bool]]) =
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Vec((a zip b) map { case (x, y) => Vec((x zip y) map { case (a, b) => a && b }) })
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grantedAIO := arbitrate( requestAIO, beatsA, out.map(_.a.fire()))
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grantedBOI := mask(arbitrate(mask(requestBOI, maskOI), beatsB, in .map(_.b.fire())), maskOI)
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grantedCIO := mask(arbitrate(mask(requestCIO, maskIO), beatsC, out.map(_.c.fire())), maskIO)
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grantedDOI := arbitrate( requestDOI, beatsD, in .map(_.d.fire()))
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grantedEIO := mask(arbitrate(mask(requestEIO, maskIO), beatsE, out.map(_.e.fire())), maskIO)
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def arbitrate(request: Seq[Seq[Bool]], beats: Seq[UInt], progress: Seq[Bool]) = {
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request foreach { row => require (row.size == progress.size) } // consistent # of resources
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request foreach { resources => // only one resource is requested
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val prefixOR = resources.scanLeft(Bool(false))(_ || _).init
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assert (!(prefixOR zip resources).map{case (a, b) => a && b}.reduce(_ || _))
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}
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transpose((transpose(request) zip progress).map { case (r,p) => arbitrate1(r, beats, p) })
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}
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def arbitrate1(requests: Vec[Bool], beats: Seq[UInt], progress: Bool) = {
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require (requests.size == beats.size) // consistent # of requesters
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val beatsLeft = RegInit(UInt(0))
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val idle = beatsLeft === UInt(0)
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// Apply policy to select which requester wins
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val winners = Vec(policy(requests, idle))
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// Supposing we take the winner as input, how many beats must be sent?
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val initBeats = Mux1H(winners, beats)
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// What is the counter state before progress?
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val todoBeats = Mux(idle, initBeats, beatsLeft)
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// Apply progress and register the result
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beatsLeft := todoBeats - progress.asUInt
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assert (!progress || todoBeats =/= UInt(0)) // underflow should be impossible
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// The previous arbitration state of the resource
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val state = RegInit(Vec.fill(requests.size)(Bool(false)))
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// Only take a new value while idle
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val muxState = Mux(idle, winners, state)
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state := muxState
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muxState
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}
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})
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}
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