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tilelink2: add a stub SRAM manager

This commit is contained in:
Wesley W. Terpstra 2016-08-26 14:16:17 -07:00
parent a87c2d13e2
commit 0ff33a31a4

View File

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// See LICENSE for license details.
package uncore.tilelink2
import Chisel._
class TLRAM(address: AddressSet, beatBytes: Int = 4) extends TLFactory
{
val node = TLManagerNode(beatBytes, TLManagerParameters(
address = List(address),
regionType = RegionType.UNCACHED,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))) // requests are handled in order
lazy val module = Module(new TLModule(this) {
val io = new Bundle {
val in = node.bundleIn
}
// do stuff
})
}