hasti: fix test SRAM depth
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@ -474,7 +474,7 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
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// The mask and address during the address phase
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val a_request = io.hsel && (io.htrans === HTRANS_NONSEQ || io.htrans === HTRANS_SEQ)
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val a_mask = Wire(UInt(width = hastiDataBytes))
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val a_address = io.haddr >> UInt(hastiAlignment)
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val a_address = io.haddr(depth-1, hastiAlignment)
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val a_write = io.hwrite
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// for backwards compatibility with chisel2, we needed a static width in definition
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@ -507,7 +507,7 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
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val p_wdata = holdUnless(d_wdata, p_latch_d)
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// Use single-ported memory with byte-write enable
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val mem = SeqMem(depth, Vec(hastiDataBytes, Bits(width = 8)))
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val mem = SeqMem(1 << (depth-hastiAlignment), Vec(hastiDataBytes, Bits(width = 8)))
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// Decide is the SRAM port is used for reading or (potentially) writing
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val read = ready && a_request && !a_write
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