riscv/rocket-chip
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rocket: support asynchronous external busses

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Wesley W. Terpstra 2016-07-18 14:09:10 -07:00 committed by Howard Mao
parent 19b44ec95b
commit 9ae23f18bd
3 changed files with 26 additions and 5 deletions
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4
src/main/scala/Configs.scala
View File

@ -191,6 +191,7 @@ class BaseConfig extends Config (
case UseVM => true
case UseUser => true
case UseDebug => true
case AsyncDebugBus => false
case NBreakpoints => 1
case UsePerfCounters => true
case FastLoadWord => true
@ -216,6 +217,7 @@ class BaseConfig extends Config (
true
}
case NExtInterrupts => 2
case AsyncMMIOChannels => false
case ExtMMIOPorts => AddrMap()
/*
AddrMap(
@ -225,6 +227,7 @@ class BaseConfig extends Config (
case NExtMMIOAXIChannels => 0
case NExtMMIOAHBChannels => 0
case NExtMMIOTLChannels => 0
case AsyncBusChannels => false
case NExtBusAXIChannels => 0
case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
@ -297,6 +300,7 @@ class BaseConfig extends Config (
}
case TLKey("MMIO_Outermost") => site(TLKey("L2toMMIO")).copy(dataBeats = site(MIFDataBeats))
case NTiles => Knob("NTILES")
case AsyncMemChannels => false
case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
case TMemoryChannels => BusType.AXI
case NBanksPerMemoryChannel => Knob("NBANKS_PER_MEM_CHANNEL")

25
src/main/scala/RocketChip.scala
View File

@ -26,6 +26,7 @@ object BusType {
}
/** Number of memory channels */
case object AsyncMemChannels extends Field[Boolean]
case object NMemoryChannels extends Field[Int]
case object TMemoryChannels extends Field[BusType.EnumVal]
/** Number of banks per memory channel */
@ -35,10 +36,12 @@ case object BankIdLSB extends Field[Int]
/** Number of outstanding memory requests */
case object NOutstandingMemReqsPerChannel extends Field[Int]
/** Number of exteral MMIO ports */
case object AsyncMMIOChannels extends Field[Boolean]
case object ExtMMIOPorts extends Field[AddrMap]
case object NExtMMIOAXIChannels extends Field[Int]
case object NExtMMIOAHBChannels extends Field[Int]
case object NExtMMIOTLChannels extends Field[Int]
case object AsyncBusChannels extends Field[Boolean]
case object NExtBusAXIChannels extends Field[Int]
/** Function for building some kind of coherence manager agent */
case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
@ -52,6 +55,7 @@ case object NExtInterrupts extends Field[Int]
case object PLICKey extends Field[PLICConfig]
/** Number of clock cycles per RTC tick */
case object RTCPeriod extends Field[Int]
case object AsyncDebugBus extends Field[Boolean]
case object UseStreamLoopback extends Field[Boolean]
case object StreamLoopbackSize extends Field[Int]
@ -92,14 +96,22 @@ class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
with HasTopLevelParameters
class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
val mem_clk = if (p(AsyncMemChannels)) Some(Vec(nMemChannels, Clock(INPUT))) else None
val mem_rst = if (p(AsyncMemChannels)) Some(Vec(nMemChannels, Bool (INPUT))) else None
val mem_axi = Vec(nMemAXIChannels, new NastiIO)
val mem_ahb = Vec(nMemAHBChannels, new HastiMasterIO)
val mem_tl = Vec(nMemTLChannels, new ClientUncachedTileLinkIO()(outermostParams))
val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
val bus_clk = if (p(AsyncBusChannels)) Some(Vec(p(NExtBusAXIChannels), Clock(INPUT))) else None
val bus_rst = if (p(AsyncBusChannels)) Some(Vec(p(NExtBusAXIChannels), Bool (INPUT))) else None
val bus_axi = Vec(p(NExtBusAXIChannels), new NastiIO).flip
val mmio_clk = if (p(AsyncMMIOChannels)) Some(Vec(p(NExtMMIOAXIChannels), Clock(INPUT))) else None
val mmio_rst = if (p(AsyncMMIOChannels)) Some(Vec(p(NExtMMIOAXIChannels), Bool (INPUT))) else None
val mmio_axi = Vec(p(NExtMMIOAXIChannels), new NastiIO)
val mmio_ahb = Vec(p(NExtMMIOAHBChannels), new HastiMasterIO)
val mmio_tl = Vec(p(NExtMMIOTLChannels), new ClientUncachedTileLinkIO()(outermostMMIOParams))
val debug_clk = if (p(AsyncDebugBus)) Some(Clock(INPUT)) else None
val debug_rst = if (p(AsyncDebugBus)) Some(Bool(INPUT)) else None
val debug = new DebugBusIO()(p).flip
}
@ -185,15 +197,20 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
uncore.io.tiles_cached <> tileList.map(_.io.cached).flatten
uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
uncore.io.interrupts <> io.interrupts
uncore.io.debugBus <> io.debug
uncore.io.debugBus <>
(if (p(AsyncDebugBus)) AsyncDebugBusFrom(io.debug_clk.get, io.debug_rst.get, io.debug) else io.debug)
io.mmio_axi <> uncore.io.mmio_axi
for (i <- 0 until p(NExtMMIOAXIChannels))
io.mmio_axi(i) <> (if (p(AsyncMMIOChannels)) AsyncNastiTo((io.mmio_clk.get)(i), (io.mmio_rst.get)(i), uncore.io.mmio_axi(i)) else uncore.io.mmio_axi(i))
io.mmio_ahb <> uncore.io.mmio_ahb
io.mmio_tl <> uncore.io.mmio_tl
io.mem_axi <> uncore.io.mem_axi
for (i <- 0 until nMemAXIChannels)
io.mem_axi(i) <> (if (p(AsyncMemChannels)) AsyncNastiTo((io.mem_clk.get)(i), (io.mem_rst.get)(i), uncore.io.mem_axi(i)) else uncore.io.mem_axi(i))
io.mem_ahb <> uncore.io.mem_ahb
io.mem_tl <> uncore.io.mem_tl
uncore.io.bus_axi <> io.bus_axi
for (i <- 0 until p(NExtBusAXIChannels))
uncore.io.bus_axi(i) <> (if (p(AsyncDebugBus)) AsyncNastiFrom((io.bus_clk.get)(i), (io.bus_rst.get)(i), io.bus_axi(i)) else io.bus_axi(i))
}
/** Wrapper around everything that isn't a Tile.

2
uncore

@ -1 +1 @@
Subproject commit 5d9c9677d30e79a1c21a5dc7b787563cfd700e28
Subproject commit 1ba9dd64af5627d4d58c4716363ece3b0676eff7