tilelink2: decouple BaseNode from TileLink bus (so it can be reused)
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@ -11,9 +11,9 @@ abstract class LazyModule
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private val bindings = ListBuffer[() => Unit]()
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// Use as: connect(source -> sink, source2 -> sink2, ...)
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def connect(edges: (TLBaseNode, TLBaseNode)*)(implicit sourceInfo: SourceInfo) = {
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def connect[PO, PI, EO, EI, B <: Bundle](edges: (BaseNode[PO, PI, EO, EI, B], BaseNode[PO, PI, EO, EI, B])*)(implicit sourceInfo: SourceInfo) = {
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edges.foreach { case (source, sink) =>
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bindings += sink.edge(source)
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bindings += (source edge sink)
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}
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}
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@ -6,9 +6,22 @@ import Chisel._
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import scala.collection.mutable.ListBuffer
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import chisel3.internal.sourceinfo.SourceInfo
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class TLBaseNode(
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private val clientFn: Option[Seq[TLClientPortParameters] => TLClientPortParameters],
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private val managerFn: Option[Seq[TLManagerPortParameters] => TLManagerPortParameters],
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// PI = PortInputParameters
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// PO = PortOutputParameters
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// EI = EdgeInput
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// EO = EdgeOutput
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abstract class NodeImp[PO, PI, EO, EI, B <: Bundle]
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{
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def edgeO(po: PO, pi: PI): EO
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def edgeI(po: PO, pi: PI): EI
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def bundleO(eo: Seq[EO]): Vec[B]
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def bundleI(ei: Seq[EI]): Vec[B]
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def connect(bo: B, eo: EO, bi: B, ei: EI)(implicit sourceInfo: SourceInfo): Unit
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}
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class BaseNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(
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private val clientFn: Option[Seq[PO] => PO],
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private val managerFn: Option[Seq[PI] => PI],
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private val numClientPorts: Range.Inclusive,
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private val numManagerPorts: Range.Inclusive)
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{
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@ -24,50 +37,44 @@ class TLBaseNode(
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require (noClients || clientFn.isDefined)
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require (noManagers || managerFn.isDefined)
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private val accClientPorts = ListBuffer[TLBaseNode]()
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private val accManagerPorts = ListBuffer[TLBaseNode]()
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private val accClientPorts = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
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private val accManagerPorts = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
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private var clientRealized = false
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private var managerRealized = false
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private lazy val clientPorts = { clientRealized = true; require (numClientPorts.contains(accClientPorts.size)); accClientPorts.result() }
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private lazy val managerPorts = { managerRealized = true; require (numManagerPorts.contains(accManagerPorts.size)); accManagerPorts.result() }
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private lazy val clientParams : Option[TLClientPortParameters] = clientFn.map(_(managerPorts.map(_.clientParams.get)))
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private lazy val managerParams : Option[TLManagerPortParameters] = managerFn.map(_(clientPorts.map(_.managerParams.get)))
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private lazy val clientParams : Option[PO] = clientFn.map(_(managerPorts.map(_.clientParams.get)))
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private lazy val managerParams : Option[PI] = managerFn.map(_(clientPorts.map(_.managerParams.get)))
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lazy val edgesOut = clientPorts.map { n => new TLEdgeOut(clientParams.get, n.managerParams.get) }
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lazy val edgesIn = managerPorts.map { n => new TLEdgeIn (n.clientParams.get, managerParams.get) }
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lazy val edgesOut = clientPorts.map { n => imp.edgeO(clientParams.get, n.managerParams.get) }
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lazy val edgesIn = managerPorts.map { n => imp.edgeI(n.clientParams.get, managerParams.get) }
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lazy val bundleOut = { require (!edgesOut.isEmpty); Vec(edgesOut.size, TLBundle(edgesOut.map(_.bundle).reduce(_.union(_)))) }
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lazy val bundleIn = { require (!edgesIn .isEmpty); Vec(edgesIn .size, TLBundle(edgesIn .map(_.bundle).reduce(_.union(_)))).flip }
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lazy val bundleOut = imp.bundleO(edgesOut)
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lazy val bundleIn = imp.bundleI(edgesIn)
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def connectOut = bundleOut
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def connectIn = bundleIn
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protected[tilelink2] def edge(x: TLBaseNode)(implicit sourceInfo: SourceInfo) = {
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require (!noManagers)
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require (!managerRealized)
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require (!x.noClients)
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require (!x.clientRealized)
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val i = accManagerPorts.size
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val j = x.accClientPorts.size
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accManagerPorts += x
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x.accClientPorts += this
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// source.edge(sink)
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protected[tilelink2] def edge(x: BaseNode[PO, PI, EO, EI, B])(implicit sourceInfo: SourceInfo) = {
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require (!noClients)
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require (!clientRealized)
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require (!x.noManagers)
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require (!x.managerRealized)
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val i = x.accManagerPorts.size
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val o = accClientPorts.size
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accClientPorts += x
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x.accManagerPorts += this
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() => {
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val in = connectIn(i)
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val out = x.connectOut(j)
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TLMonitor.legalize(out, x.edgesOut(j), in, edgesIn(i), sourceInfo)
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in <> out
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val mask = ~UInt(edgesIn(i).manager.beatBytes - 1)
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in .a.bits.address := (mask & out.a.bits.address)
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out.b.bits.address := (mask & in .b.bits.address)
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in .c.bits.address := (mask & out.c.bits.address)
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imp.connect(connectOut(o), edgesOut(o), x.connectIn(i), x.edgesIn(i))
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}
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}
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}
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class TLClientNode(
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params: TLClientParameters,
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numPorts: Range.Inclusive = 1 to 1) extends TLBaseNode(
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numPorts: Range.Inclusive = 1 to 1) extends BaseNode(TLImp)(
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clientFn = Some {case Seq() => TLClientPortParameters(Seq(params))},
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managerFn = None,
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numClientPorts = numPorts,
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@ -86,7 +93,7 @@ object TLClientNode
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class TLManagerNode(
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beatBytes: Int,
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params: TLManagerParameters,
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numPorts: Range.Inclusive = 1 to 1) extends TLBaseNode(
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numPorts: Range.Inclusive = 1 to 1) extends BaseNode(TLImp)(
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clientFn = None,
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managerFn = Some {case Seq() => TLManagerPortParameters(Seq(params), beatBytes)},
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numClientPorts = 0 to 0,
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@ -107,7 +114,7 @@ class TLAdapterNode(
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clientFn: Seq[TLClientPortParameters] => TLClientPortParameters,
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managerFn: Seq[TLManagerPortParameters] => TLManagerPortParameters,
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numClientPorts: Range.Inclusive = 1 to 1,
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numManagerPorts: Range.Inclusive = 1 to 1) extends TLBaseNode(
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numManagerPorts: Range.Inclusive = 1 to 1) extends BaseNode(TLImp)(
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clientFn = Some(clientFn),
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managerFn = Some(managerFn),
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numClientPorts = numClientPorts,
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@ -122,7 +129,7 @@ object TLAdapterNode
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numManagerPorts: Range.Inclusive = 1 to 1) = new TLAdapterNode(clientFn, managerFn, numClientPorts, numManagerPorts)
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}
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class TLOutputNode extends TLBaseNode(
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class TLOutputNode extends BaseNode(TLImp)(
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clientFn = Some({case Seq(x) => x}),
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managerFn = Some({case Seq(x) => x}),
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numClientPorts = 1 to 1,
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@ -137,7 +144,7 @@ object TLOutputNode
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def apply() = new TLOutputNode()
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}
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class TLInputNode extends TLBaseNode(
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class TLInputNode extends BaseNode(TLImp)(
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clientFn = Some({case Seq(x) => x}),
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managerFn = Some({case Seq(x) => x}),
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numClientPorts = 1 to 1,
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@ -3,6 +3,7 @@
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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class TLEdge(
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client: TLClientPortParameters,
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@ -430,3 +431,26 @@ class TLEdgeIn(
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d
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}
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}
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object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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{
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def edgeO(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(po, pi)
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def edgeI(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(po, pi)
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def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = {
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require (!eo.isEmpty)
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Vec(eo.size, TLBundle(eo.map(_.bundle).reduce(_.union(_))))
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}
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def bundleI(ei: Seq[TLEdgeIn]): Vec[TLBundle] = {
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require (!ei.isEmpty)
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Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
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}
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def connect(bo: TLBundle, eo: TLEdgeOut, bi: TLBundle, ei: TLEdgeIn)(implicit sourceInfo: SourceInfo): Unit = {
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TLMonitor.legalize(bo, eo, bi, ei, sourceInfo)
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bi <> bo
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val mask = ~UInt(ei.manager.beatBytes - 1)
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bi.a.bits.address := (mask & bo.a.bits.address)
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bo.b.bits.address := (mask & bi.b.bits.address)
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bi.c.bits.address := (mask & bo.c.bits.address)
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}
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}
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