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riscv
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rocket-chip
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fa8317fec1c3ad50449a80bd5e3d9179f021439c
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Wesley W. Terpstra
fa8317fec1
debug: add clock crossing primitives
2016-07-19 14:52:43 -07:00
uncore
debug: add clock crossing primitives
2016-07-19 14:52:43 -07:00
Description
Rocket Chip Generator (
https://github.com/freechipsproject/rocket-chip
)
13
MiB
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%