riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman ba08255450 bump rocket 2016-07-14 22:11:19 -07:00
Andrew Waterman 768403f8fa Bump rocket; remove ICacheBufferWays parameter 2016-07-14 12:50:16 -07:00
Andrew Waterman 32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al 2016-07-07 21:23:49 -07:00
Andrew Waterman 2a146155fc Update to new priv-1.9 PTE format 2016-07-06 10:15:59 -07:00
Andrew Waterman 85808f8cbb Clean up PseudoLRU code 2016-07-02 15:09:12 -07:00
Andrew WatermanandHoward Mao f1cbb2ff77 Turn up optimization for Verilator compilation 2016-06-28 14:12:46 -07:00
Andrew Waterman c725a78086 Merge RTC into PRCI 2016-06-27 23:08:29 -07:00
Andrew Waterman 97e74aec3a Merge RTC and PRCI 2016-06-27 23:06:07 -07:00
Andrew Waterman 87a4858aa6 Exit from testbench, not C code 
Otherwise, we don't get coverage data from the simulator.
 2016-06-23 20:54:07 -07:00
Andrew Waterman 568bfa6c50 Purge legacy HTIF things 
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
 2016-06-23 13:23:57 -07:00
Andrew Waterman 354b81c8fe Remove legacy HTIF things 
The SCR file is gone, too, because it is tightly coupled.  The
general concept could be revived as a module that somehow connects
to (or is contained by) the debug module.
 2016-06-23 13:17:11 -07:00
Andrew Waterman 2d44be747a Fix groundtest without HTIF 2016-06-23 12:17:26 -07:00
Andrew Waterman 30331fcaeb Remove HTIF; use debug module for testing in simulation 2016-06-23 00:32:05 -07:00
Andrew Waterman f57524e0c1 Remove FENCE.I from debug ROM; specialize for RV64 2016-06-23 00:01:26 -07:00
Andrew Waterman 4a8e6c773a Fix +verbose flag for verilator 2016-06-17 21:09:08 -07:00
Andrew Waterman b79db89c03 Update breakpoint spec 2016-06-09 19:13:55 -07:00
Andrew Waterman 9e86b9efc9 Add provisional breakpoint support 2016-06-08 22:34:19 -07:00
Andrew Waterman 2c17f828b6 bump chisel and rocket 2016-06-06 21:36:51 -07:00
Andrew Waterman dd85f2410f Avoid need for cloneType 2016-06-05 23:47:56 -07:00
Andrew Waterman 631e3e2dd9 Make PRCI a singleton, not per-tile 
Some stuff is densely packed in the address space (e.g. IPI regs),
so needs to be on the same TileLink slave port
 2016-06-05 23:06:21 -07:00
Andrew Waterman be7500e4a9 Update PLIC addr map 2016-06-05 23:04:51 -07:00
Andrew Waterman 2e88ffc364 Cope with changes to AddrMap 2016-06-03 13:48:09 -07:00
Andrew Waterman f1745bf142 Allow PLIC nPriorities=0 (priority fixed at 1) 2016-06-02 13:48:29 -07:00
Andrew Waterman b7ca2145b3 Fix PLIC control bug when !grant.ready 2016-06-02 13:47:59 -07:00
Andrew Waterman 0866b4c045 Can't assign to Vec literals 2016-06-01 23:36:34 -07:00
Andrew Waterman 20e1de08da Avoid chisel2 pitfall 
This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3.  D'oh.
 2016-06-01 23:35:49 -07:00
Andrew Waterman 5629fb62bf Avoid bitwise sub-assignment 2016-06-01 21:59:02 -07:00
Andrew Waterman 9518b3d589 Fix arithmetic in ROM row count 2016-06-01 21:59:02 -07:00
Andrew Waterman 8e80d1ec80 Avoid floating-point arithmetic where integers suffice 2016-06-01 21:59:02 -07:00
Andrew Waterman 1311e78d3f Add blocking D$ flush support 2016-05-31 19:28:41 -07:00
Andrew Waterman 6d82c0d156 Add M_FLUSH_ALL command 2016-05-31 19:25:31 -07:00
Andrew Waterman 44a216038f Use more generic TileLinkWidthAdapter 2016-05-27 13:38:13 -07:00
Andrew Waterman 8afdd7e3da Work around PutBlocks draining into data array prematurely 2016-05-26 23:08:05 -07:00
Andrew Waterman 10f0e13c25 Use more parsimonious queue depths 2016-05-26 18:04:22 -07:00
Andrew Waterman 3cc236e9c4 By default, use same TileLink width everywhere 
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
 2016-05-26 18:04:01 -07:00
Andrew Waterman 391a9b9110 Use buses, rather than crossbars, by default in TLInterconnect 
We should eventually parameterize this, of course.
 2016-05-26 16:10:42 -07:00
Andrew Waterman b6d26e90f8 Add generic TileLink width adapter 2016-05-26 15:59:42 -07:00
Andrew Waterman 8139f71dfb Work around Chisel2 bug 
This code is correct, but Chisel2 erroneously flags it as a Chisel3
compatibility error because it looks like Vec(Reg) when factor=1.
 2016-05-26 12:37:31 -07:00
Andrew Waterman 22568de5f3 Work around another zero-width wire limitation 2016-05-25 21:42:02 -07:00
Andrew Waterman e2755a0f0a Work around zero-width wire limitation in HTIF 2016-05-25 20:39:53 -07:00
Andrew Waterman 3e238adc67 rtc: fix acquire message type check 2016-05-25 20:37:48 -07:00
Andrew Waterman ec0d178010 Support M-mode-only implementations 2016-05-25 15:40:53 -07:00
Andrew Waterman da105a5944 Don't allow travis to recurse through submodules 2016-05-25 13:27:49 -07:00
Andrew Waterman e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Andrew Waterman a8462d3cfc bump chisel 2016-05-25 11:09:50 -07:00
Andrew Waterman 88cc91db75 Ignore way_en in MetadataArray for direct-mapped caches 2016-05-24 15:47:09 -07:00
Andrew Waterman 684d902059 Fix PLIC instantiation when S-mode is disabled 2016-05-13 11:22:46 -07:00
Andrew Waterman 6aa708bcee Disable MMIO by default to avoid disconnected nets 2016-05-11 13:12:39 -07:00
Andrew Waterman 533b229175 Improve PLIC QoR 2016-05-10 17:03:56 -07:00
Andrew Waterman fbff46d27d bump rocket 2016-05-10 10:57:03 -07:00
Andrew Waterman aac89ca1f0 Add PLIC 2016-05-10 00:27:31 -07:00
Andrew Waterman e15e9c5085 First draft of interrupt controller 2016-05-10 00:25:13 -07:00
Andrew WatermanandHoward Mao 8b06947446 Run bmarks faster (hopefully) 2016-05-04 22:47:34 -07:00
Andrew Waterman 15f4af19cf Remove HTIF CPU port 2016-05-03 13:55:59 -07:00
Andrew Waterman c7c8ae5468 Instantiate PRCI block 2016-05-02 18:08:33 -07:00
Andrew Waterman cc4102f8de Add trivial version of PRCI block 
It doesn't really do anything besides deliver deliver IPIs yet.
 2016-05-02 17:49:10 -07:00
Andrew Waterman 6d1e82bddf Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port 2016-05-02 15:21:55 -07:00
Andrew Waterman 72731de25a Take a stab at the PRCI-Rocket interface 2016-05-02 15:20:33 -07:00
Andrew Waterman c4d2d29e80 Stub out debug module, rather than leaving it floating 2016-04-30 22:37:39 -07:00
Andrew Waterman 46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
Andrew Waterman 695c4c5096 Support both Get and GetBlock on ROMSlave 2016-04-30 17:34:12 -07:00
Andrew Waterman d0aa4c722d More WIP on new memory map 2016-04-28 16:15:31 -07:00
Andrew Waterman 1df68a25fd Address Map refactoring 2016-04-28 16:08:58 -07:00
Andrew Waterman 1f211b37df WIP on new memory map 2016-04-27 14:57:54 -07:00
Andrew Waterman 81ff127dc3 Clean up TileLinkRecursiveInterconnect a bit 2016-04-27 14:53:11 -07:00
Andrew Waterman 87cecc336f Add new RTC as TileLink slave, not AXI master 2016-04-27 11:55:35 -07:00
Andrew Waterman eb0b5ec61e Remove stats CSR 2016-04-27 00:16:21 -07:00
Andrew Waterman 9044a4a4b7 Replace NastiROM with ROMSlave, which uses TileLink 
I'm not wedded to the name.
 2016-04-27 00:15:30 -07:00
Andrew Waterman 356efe2fd5 Simplify TileLink Narrower 
It's not necessary to use addr_beat to determine where to put the Grant
data.  Just stripe it across all lanes.

This also gets rid of a dependence on addr_beat in Grant.  If we move
towards a regime where TileLink is only narrowed, not widened, we may
be able to drop the field altogether.
 2016-04-26 16:44:54 -07:00
Andrew WatermanandHenry Cook c4c6bd1040 Bump rocket. 
Closes #84.
 2016-04-01 18:20:32 -07:00
Andrew WatermanandHenry Cook b43a85e2e8 Make ExampleSmallConfig/DefaultRV32Config smaller 2016-04-01 18:18:08 -07:00
Andrew WatermanandHenry Cook 6878e3265f Default RowBits to TileLink width, not XLen 2016-04-01 18:18:08 -07:00
Andrew WatermanandHenry Cook 46d7dceb1e Disable printf/assert during reset 2016-04-01 18:18:08 -07:00
Andrew WatermanandHenry Cook cd9e07d8e7 Update sbt to 0.13.11 2016-04-01 18:18:08 -07:00
Andrew WatermanandHenry Cook bd3dba7f66 Fix LR/SC livelock bug 
Closes #74.
 2016-04-01 18:18:08 -07:00
Andrew Waterman 8957b5e973 Improve simulation speed of BasicCrossbar 2016-04-01 13:28:11 -07:00
Andrew Waterman 6c48dc3471 Use more sensible knob values for SmallConfig 2016-03-25 14:18:24 -07:00
Andrew Waterman cce89f5fbc Bump rocket 2016-03-25 14:18:15 -07:00
Andrew Waterman 9dc0cbdfa4 WIP on privileged spec v1.9 2016-03-14 18:03:33 -07:00
Andrew Waterman 25091003af Add RV32 test/configuration options 
These won't actually work until further commits.  Rocket RV32 support
is complete, but on the priv-1.9 branch.
 2016-03-10 17:40:21 -08:00
Andrew Waterman 2eafc4c8f3 Extend AMOALU to support RV32 2016-03-10 17:32:23 -08:00
Andrew Waterman c28d115b30 Chisel3 compatibility fix 2016-03-10 17:32:23 -08:00
Andrew Waterman 7a75a03123 tabs are evil 2016-03-10 14:18:56 -08:00
Andrew Waterman 36f2e6504c Fix width of NastiROM rows, preventing out-of-range extraction 2016-03-03 16:57:16 -08:00
Andrew Waterman fdd19145e9 bump chisel/hardfloat/junctions/uncore submodules 2016-01-17 01:50:04 -08:00
Andrew Waterman 2946bc928e Avoid muxing between bundles of different size 2016-01-16 19:01:24 -08:00
Andrew Waterman fc638c6339 Chisel3 compatibility fixes 2016-01-12 16:28:05 -08:00
Andrew Waterman 603db5e271 Chisel3 compatibility; new NaNs; new MIPI behavior 2016-01-12 16:25:03 -08:00
Andrew Waterman 0b90b8fe5f Avoid zero-width wire case :-/ 2016-01-12 15:32:29 -08:00
Andrew Waterman a953ff384a Chisel3 compatibility: use more concrete types 2016-01-12 15:32:14 -08:00
Andrew Waterman e0d849fec5 Fix zscale testing 
Use the following command in vsim:

make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
 2015-12-01 17:31:48 -08:00
Andrew Waterman 5eeb8969f6 fix zscale build (run still fails) 2015-12-01 16:20:34 -08:00
Andrew Waterman e25a020e60 Construct device tree ROM in MMIO region 
Rebuild riscv-tools for this to work!
 2015-11-25 21:23:37 -08:00
Andrew Waterman e52685f2e9 Fix LoadGen zero flag 2015-11-25 20:52:30 -08:00
Andrew Waterman 27df04354f Add ROM with NASTI interface 2015-11-25 20:04:31 -08:00
Andrew Waterman 49d93da87e Factor out more common zscale code 2015-11-24 19:17:21 -08:00
Andrew Waterman 52b25c3da0 Factor out more common zscale code 2015-11-24 18:34:03 -08:00
Andrew Waterman 1761db3272 Factor out some common code from zscale 2015-11-24 18:14:06 -08:00
Andrew Waterman 57e82442a1 Make LoadGen and StoreGen generic 2015-11-24 18:12:42 -08:00
Andrew Waterman 5195a5b891 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:53:14 -08:00