riscv/rocket-chip
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Fix groundtest without HTIF

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This commit is contained in:
Andrew Waterman 2016-06-23 12:17:26 -07:00
parent 30331fcaeb
commit 2d44be747a
6 changed files with 25 additions and 22 deletions
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2
chisel2

@ -1 +1 @@
Subproject commit e9e5bb28ac230ab7c54aab9ca30fbe164bbb84be
Subproject commit 257bd9732cc977479d1bdc91742dee32cc47e8a9

2
chisel3

@ -1 +1 @@
Subproject commit 70a41e5aed5dc3bc52133aecf46049a5946d33fe
Subproject commit 2e9b41cafe9158f20ecb03ae9eabecb82e557829

34
csrc/emulator.cc
View File

@ -25,6 +25,7 @@
#include "emulator_type.h"
static dtm_t* dtm;
static uint64_t trace_count = 0;
bool verbose;
void handle_sigterm(int sig)
@ -32,11 +33,15 @@ void handle_sigterm(int sig)
dtm->stop();
}
double sc_time_stamp()
{
return trace_count;
}
int main(int argc, char** argv)
{
unsigned random_seed = (unsigned)time(NULL) ^ (unsigned)getpid();
uint64_t max_cycles = -1;
uint64_t trace_count = 0;
uint64_t start = 0;
int ret = 0;
const char* vcd = NULL;
@ -179,7 +184,7 @@ int main(int argc, char** argv)
#include TBFRAG
while (!dtm->done() && (trace_count >> 1) < max_cycles && ret == 0)
while (!dtm->done() && trace_count < max_cycles && ret == 0)
{
for (int i = 0; i < N_MEM_CHANNELS; i++) {
value(mem_ar_ready[i]) = mm[i]->ar_ready();
@ -212,13 +217,12 @@ int main(int argc, char** argv)
tile.eval();
// make sure we dump on cycle 0 to get dump_init
#if VM_TRACE
if (tfp && ((trace_count >> 1) == 0 || (trace_count >> 1) >= start))
tfp->dump(trace_count);
if (tfp && (trace_count == 0 || trace_count >= start))
tfp->dump(trace_count * 2);
#endif
#endif
trace_count++;
} catch (std::runtime_error& e) {
max_cycles = trace_count >> 1; // terminate cleanly after this cycle
max_cycles = trace_count; // terminate cleanly after this cycle
ret = 1;
std::cerr << e.what() << std::endl;
}
@ -258,20 +262,20 @@ int main(int argc, char** argv)
}
#ifndef VERILATOR
if (verbose && (trace_count >> 1) >= start)
if (verbose && trace_count >= start)
tile.print(stderr);
// make sure we dump on cycle 0 to get dump_init
if (vcd && ((trace_count >> 1) == 0 || (trace_count >> 1) >= start))
tile.dump(vcdfile, trace_count >> 1);
if (vcd && (trace_count == 0 || trace_count >= start))
tile.dump(vcdfile, trace_count);
tile.clock_hi(LIT<1>(0));
#else
tile.clk = 1;
tile.eval();
#if VM_TRACE
if (tfp && ((trace_count >> 1) == 0 || (trace_count >> 1) >= start))
tfp->dump(trace_count);
if (tfp && (trace_count == 0 || trace_count >= start))
tfp->dump(trace_count * 2 + 1);
#endif
#endif
trace_count++;
@ -288,17 +292,17 @@ int main(int argc, char** argv)
if (dtm->exit_code())
{
fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", dtm->exit_code(), random_seed, trace_count >> 1);
fprintf(stderr, "*** FAILED *** (code = %d, seed %d) after %ld cycles\n", dtm->exit_code(), random_seed, trace_count);
ret = dtm->exit_code();
}
else if ((trace_count >> 1) == max_cycles)
else if (trace_count == max_cycles)
{
fprintf(stderr, "*** FAILED *** (timeout, seed %d) after %ld cycles\n", random_seed, trace_count >> 1);
fprintf(stderr, "*** FAILED *** (timeout, seed %d) after %ld cycles\n", random_seed, trace_count);
ret = 2;
}
else if (verbose || print_cycles)
{
fprintf(stderr, "Completed after %ld cycles\n", trace_count >> 1);
fprintf(stderr, "Completed after %ld cycles\n", trace_count);
}
delete dtm;

2
firrtl

@ -1 +1 @@
Subproject commit 860b04eff7758c3efae09fb0b5b908abad3b4593
Subproject commit 85dc973ecc3042370f218b77dfa0990fde6c2e0f

2
groundtest

@ -1 +1 @@
Subproject commit 45fd2af56be99ff2f9f04b7acc8e402d2efb770b
Subproject commit e636d7a4ff1a6fe11f6fd4ee8ad2588becae68ae

5
src/main/scala/TestConfigs.scala
View File

@ -36,8 +36,7 @@ class WithGroundTest extends Config(
(r: Bool, p: Parameters) =>
Module(new GroundTestTile(i, r)(p.alterPartial({
case TLId => "L1toL2"
case NUncachedTileLinkPorts =>
(if (i == 0) 1 else 0) + p(GroundTestUncachedClients)
case NUncachedTileLinkPorts => p(GroundTestUncachedClients)
})))
}
}
@ -76,7 +75,7 @@ class WithComparator extends Config(
Seq((r: Bool, p: Parameters) => Module(new ComparatorTile(r)(
p.alterPartial({
case TLId => "L1toL2"
case NUncachedTileLinkPorts => 1 + site(ComparatorKey).targets.size
case NUncachedTileLinkPorts => site(ComparatorKey).targets.size
}))))
}
case ComparatorKey => ComparatorParameters(