Howard Mao
ce242b8f3f
Merge remote-tracking branch 'uncore/master' into mono-repo
2016-07-28 11:23:31 -07:00
Howard Mao
aefba04fb3
get rid of submodules in preparation for merging
2016-07-28 11:21:08 -07:00
Howard Mao
6de2a3e3b1
get rid of fpga-zynq submodule
2016-07-28 11:07:47 -07:00
Howard Mao
fe51a35fa9
a few more submodule bumps
2016-07-28 09:25:59 -07:00
Howard Mao
fbcc7317cf
make sure PseudoLRU is given power of 2 ways
2016-07-27 18:39:33 -07:00
Howard Mao
15d1aa9346
make sure TrackerAllocationIO addr_block has correct direction set
2016-07-27 16:47:22 -07:00
Howard Mao
9c89290efc
fix LRSC issue (fixes issue #86 )
2016-07-26 22:25:04 -07:00
Howard Mao
ecd1af326c
fix L2 deadlock bug and add more advanced trace generator
2016-07-26 12:43:08 -07:00
Howard Mao
82bbbf908d
Fix L2 Writeback deadlock issue
...
The deadlock condition occurs when the acquire tracker attempts to
request a writeback while the writeback unit is still busy and a
voluntary release for the block to be written back is coming in.
The voluntary release cannot be accepted because it conflicts with the
acquire tracker. The acquire tracker can't merge the voluntary release
because it is waiting to send the writeback. The writeback can't
progress because the release it is waiting on is behind the voluntary
release.
The solution to this is to break the atomicity guarantee between the
acquire tracker and the writeback unit. This allows the voluntary
release tracker to take the voluntary release before the writeback unit
accepts the conflicting request. This causes a potential race condition
for the metadata array. The solution to this is to have the writeback
unit re-read the metadata after accepting a request.
2016-07-26 12:31:08 -07:00
Howard Mao
1063d90993
make sure L1 and L2 agree on coherence policy
2016-07-25 12:20:49 -07:00
Howard Mao
6a5b2d7f59
fix assembly tests for configurations without VMU and/or user mode
2016-07-22 17:21:57 -07:00
Wesley W. Terpstra
11ec5b2cf4
bram: don't deal with multibeat; rely on the fragmenter
2016-07-22 14:51:05 -07:00
Wesley W. Terpstra
a52d418439
fragmenter: support multi-beat get/put via fragmenting to single-beat operations
2016-07-22 14:48:22 -07:00
Howard Mao
75347eed56
some fixes and cleanup to stateless bridge
2016-07-21 19:51:26 -07:00
Howard Mao
9168f35971
clean up the requirements in StatelessBridge
...
* No need to check that release ID bits and acquire ID bits the same
* Check that inner and outer coherence policies match
2016-07-21 19:41:56 -07:00
Howard Mao
12067a3b8d
make sure outer probe and finish lines are disconnected
2016-07-21 15:15:44 -07:00
Howard Mao
c38dff0855
add some more warnings about the StatelessBridge
2016-07-21 15:07:10 -07:00
Megan Wachs
c31c650def
If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge.
2016-07-21 13:54:28 -07:00
Megan Wachs
eb9e998c08
Add ManagerToClientStatelessBridge
2016-07-21 13:49:16 -07:00
Howard Mao
0a1cd64786
fix number of builtin Acquire types
2016-07-21 13:45:20 -07:00
Howard Mao
ffe17cbb2b
bump uncore for L2 bugfix
2016-07-21 12:35:38 -07:00
Howard Mao
20df74d138
generate more L1 voluntary releases in TraceGen
2016-07-21 12:33:55 -07:00
Howard Mao
86e31be820
fix lockup from back to back releases with data
2016-07-21 12:06:58 -07:00
Wesley W. Terpstra
9ae23f18bd
rocket: support asynchronous external busses
2016-07-19 14:52:56 -07:00
Wesley W. Terpstra
fa8317fec1
debug: add clock crossing primitives
2016-07-19 14:52:43 -07:00
Howard Mao
19b44ec95b
Bug fixes in SimpleHellaCacheIF and L2 agents
...
* SimpleHellaCacheIF now properly handles both the non-blocking data
cache and blocking data cache.
* SimpleHellaCacheIF maintains ordering of replayed requests
* L2 VoluntaryReleaseTracker sends voluntary release grant properly
* Coherence protocols now downgrade for probeCopy
2016-07-19 09:35:13 -07:00
Henry Cook
e406d1bd73
Make probeCopy have same behavior as probeDowngrade
2016-07-18 18:22:49 -07:00
Howard Mao
9eeb1112d4
fix Bufferless irel_vs_iacq_conflict signal
2016-07-18 17:38:20 -07:00
Howard Mao
e5cccc0526
don't update xact_vol_irel if not a voluntary irel
2016-07-18 17:05:23 -07:00
Howard Mao
39a1ecbf3c
switch groundtest to merged master
2016-07-18 09:34:27 -07:00
Howard Mao
e08ec42bc0
refactor groundtest unittests into separate package
2016-07-16 23:19:55 -07:00
Megan Wachs
407bc95c42
Rename MulDivUnroll to MulUnroll
2016-07-15 15:40:17 -07:00
Megan Wachs
4c26a6bc96
Create seperate Mul/Div paramters instead of UseFastMulDiv
2016-07-15 14:40:37 -07:00
Howard Mao
84098db81f
add a TileLinkTestRAM
2016-07-15 11:03:26 -07:00
Andrew Waterman
ba08255450
bump rocket
2016-07-14 22:11:19 -07:00
Andrew Waterman
768403f8fa
Bump rocket; remove ICacheBufferWays parameter
2016-07-14 12:50:16 -07:00
Howard Mao
18ea58c85f
remove unnecessary CAMs from converters
2016-07-13 12:42:50 -07:00
Howard Mao
b122a54c32
don't allow more outer IDs than inner IDs
2016-07-13 12:42:28 -07:00
Howard Mao
de1e25f3d1
reduce usage of CAMs in converters
2016-07-13 11:20:50 -07:00
Howard Mao
4c79215fde
add a script for checking comparator trace
2016-07-12 14:42:04 -07:00
Howard Mao
90bcd3dbdc
make sure DirectGroundTest testers given correct TL settings
2016-07-11 18:11:01 -07:00
Howard Mao
8f0fa11ce4
optionally export detailed status information in DirectGroundTest
2016-07-11 18:11:00 -07:00
Howard Mao
b64998ec05
make sure dramsim reads and writes occur in the order they are received
2016-07-11 18:11:00 -07:00
Howard Mao
cb2a18b533
allow direct instatiation of arbitrary non-caching groundtests
2016-07-11 18:11:00 -07:00
Howard Mao
f03ffb32a0
add top that directly tests the TL -> AXI converters
2016-07-11 18:11:00 -07:00
Howard Mao
b47f8fbc41
don't use splat and bug out if too many address map entries
2016-07-11 18:10:42 -07:00
Wesley W. Terpstra
46fc9744e2
rocket: add an AXI master port into the chip
2016-07-11 12:16:44 -07:00
Wesley W. Terpstra
8ac7fa5544
ext: support multiple external AHB/AXI ports
2016-07-11 12:16:39 -07:00
mwachs5
36720d915a
Update README.md ( #161 )
...
Correct typo in heading
2016-07-11 00:34:13 -07:00
Andrew Waterman
9751ea0f35
Fix Verilator VCD ( #157 )
2016-07-09 02:37:39 -07:00
