Remove HTIF CPU port
This commit is contained in:
2
chisel3
2
chisel3
Submodule chisel3 updated: 6183533596...0ad47ff929
2
firrtl
2
firrtl
Submodule firrtl updated: 54184c2a08...592ee2fbc5
Submodule groundtest updated: ed6b53a337...60121c4893
2
rocket
2
rocket
Submodule rocket updated: 679c9148da...9f853450de
@ -123,16 +123,11 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
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// Build an Uncore and a set of Tiles
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val innerTLParams = p.alterPartial({case TLId => "L1toL2" })
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val uncore = Module(new Uncore()(innerTLParams))
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val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) }
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val tileList = uncore.io.prci zip p(BuildTiles) map { case(prci, tile) => tile(prci.reset, p) }
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// Connect each tile to the HTIF
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for (((hl, prci), tile) <- uncore.io.htif zip uncore.io.prci zip tileList) {
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for ((prci, tile) <- uncore.io.prci zip tileList) {
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tile.io.prci <> prci
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// TODO remove HTIF
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tile.io.host.id := prci.id
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tile.io.host.reset := prci.reset
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tile.io.host.csr.req <> Queue(hl.csr.req)
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hl.csr.resp <> Queue(tile.io.host.csr.resp)
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}
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// Connect the uncore to the tile memory ports, HostIO and MemIO
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@ -162,7 +157,6 @@ class Uncore(implicit val p: Parameters) extends Module
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val mem = Vec(nMemChannels, new NastiIO)
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val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val htif = Vec(nTiles, new HtifIO).flip
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val prci = Vec(nTiles, new PRCITileIO).asOutput
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val mmio = new NastiIO
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}
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@ -174,12 +168,6 @@ class Uncore(implicit val p: Parameters) extends Module
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outmemsys.io.tiles_uncached <> io.tiles_uncached
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outmemsys.io.tiles_cached <> io.tiles_cached
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for (i <- 0 until nTiles) {
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io.htif(i).reset := htif.io.cpu(i).reset
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io.htif(i).id := htif.io.cpu(i).id
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io.htif(i).csr <> htif.io.cpu(i).csr
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}
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val addrMap = p(GlobalAddrMap)
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val addrHashMap = p(GlobalAddrHashMap)
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val scrFile = Module(new SCRFile("UNCORE_SCR", 0))
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@ -196,6 +184,9 @@ class Uncore(implicit val p: Parameters) extends Module
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io.host <> htif.io.host
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}
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// Tie off HTIF CSR ports
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htif.io.cpu.foreach { _.csr.resp.valid := Bool(false) }
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def buildMMIONetwork(implicit p: Parameters) = {
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val (ioBase, ioAddrMap) = addrHashMap.subMap("io")
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val ioAddrHashMap = new AddrHashMap(ioAddrMap, ioBase)
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