1
0

Remove HTIF CPU port

This commit is contained in:
Andrew Waterman
2016-05-03 13:55:59 -07:00
parent 487d0b356e
commit 15f4af19cf
5 changed files with 9 additions and 18 deletions

Submodule chisel3 updated: 6183533596...0ad47ff929

2
firrtl

Submodule firrtl updated: 54184c2a08...592ee2fbc5

2
rocket

Submodule rocket updated: 679c9148da...9f853450de

View File

@ -123,16 +123,11 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
// Build an Uncore and a set of Tiles
val innerTLParams = p.alterPartial({case TLId => "L1toL2" })
val uncore = Module(new Uncore()(innerTLParams))
val tileList = uncore.io.htif zip p(BuildTiles) map { case(hl, bt) => bt(hl.reset, p) }
val tileList = uncore.io.prci zip p(BuildTiles) map { case(prci, tile) => tile(prci.reset, p) }
// Connect each tile to the HTIF
for (((hl, prci), tile) <- uncore.io.htif zip uncore.io.prci zip tileList) {
for ((prci, tile) <- uncore.io.prci zip tileList) {
tile.io.prci <> prci
// TODO remove HTIF
tile.io.host.id := prci.id
tile.io.host.reset := prci.reset
tile.io.host.csr.req <> Queue(hl.csr.req)
hl.csr.resp <> Queue(tile.io.host.csr.resp)
}
// Connect the uncore to the tile memory ports, HostIO and MemIO
@ -162,7 +157,6 @@ class Uncore(implicit val p: Parameters) extends Module
val mem = Vec(nMemChannels, new NastiIO)
val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
val htif = Vec(nTiles, new HtifIO).flip
val prci = Vec(nTiles, new PRCITileIO).asOutput
val mmio = new NastiIO
}
@ -174,12 +168,6 @@ class Uncore(implicit val p: Parameters) extends Module
outmemsys.io.tiles_uncached <> io.tiles_uncached
outmemsys.io.tiles_cached <> io.tiles_cached
for (i <- 0 until nTiles) {
io.htif(i).reset := htif.io.cpu(i).reset
io.htif(i).id := htif.io.cpu(i).id
io.htif(i).csr <> htif.io.cpu(i).csr
}
val addrMap = p(GlobalAddrMap)
val addrHashMap = p(GlobalAddrHashMap)
val scrFile = Module(new SCRFile("UNCORE_SCR", 0))
@ -196,6 +184,9 @@ class Uncore(implicit val p: Parameters) extends Module
io.host <> htif.io.host
}
// Tie off HTIF CSR ports
htif.io.cpu.foreach { _.csr.resp.valid := Bool(false) }
def buildMMIONetwork(implicit p: Parameters) = {
val (ioBase, ioAddrMap) = addrHashMap.subMap("io")
val ioAddrHashMap = new AddrHashMap(ioAddrMap, ioBase)