Remove IPI network
This is now provided via MMIO.
This commit is contained in:
2
rocket
2
rocket
Submodule rocket updated: b120ba250c...4aa954799a
@ -101,8 +101,6 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
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tile.io.host.reset := Reg(next=Reg(next=hl.reset))
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tile.io.host.csr.req <> Queue(hl.csr.req)
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hl.csr.resp <> Queue(tile.io.host.csr.resp)
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hl.ipi_req <> Queue(tile.io.host.ipi_req)
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tile.io.host.ipi_rep <> Queue(hl.ipi_rep)
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hl.debug_stats_csr := tile.io.host.debug_stats_csr
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}
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@ -151,8 +149,6 @@ class Uncore(implicit val p: Parameters) extends Module
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for (i <- 0 until nTiles) {
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io.htif(i).reset := htif.io.cpu(i).reset
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io.htif(i).id := htif.io.cpu(i).id
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htif.io.cpu(i).ipi_req <> io.htif(i).ipi_req
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io.htif(i).ipi_rep <> htif.io.cpu(i).ipi_rep
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htif.io.cpu(i).debug_stats_csr <> io.htif(i).debug_stats_csr
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val csr_arb = Module(new SMIArbiter(2, xLen, csrAddrBits))
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2
uncore
2
uncore
Submodule uncore updated: 32ca8dd752...71682bb8e4
@ -25,14 +25,7 @@ module ZscaleTestHarness;
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.io_host_csr_req_bits_data({dummy, 32'd0}),
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.io_host_csr_resp_ready(1'b1),
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.io_host_csr_resp_valid(csr_resp_valid),
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.io_host_csr_resp_bits({dummy, csr_resp_bits}),
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.io_host_ipi_req_ready(1'b1),
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.io_host_ipi_req_valid(),
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.io_host_ipi_req_bits(),
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.io_host_ipi_rep_ready(),
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.io_host_ipi_rep_valid(1'b0),
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.io_host_ipi_rep_bits()
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.io_host_csr_resp_bits({dummy, csr_resp_bits})
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);
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reg [1023:0] loadmem = 0;
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