riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Add provisional breakpoint support

Browse Source
This commit is contained in:
Andrew Waterman
2016-06-08 20:21:21 -07:00
parent 73ed4ea07b
commit 9e86b9efc9
7 changed files with 7 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
chisel3

Submodule chisel3 updated: dc2175b0eb...07fa5622cc

2
firrtl

Submodule firrtl updated: 26694d3496...cc4e7e39eb

2
riscv-tools

Submodule riscv-tools updated: 0a12a54524...e9506ebc98

2
rocket

Submodule rocket updated: 40e8179ba5...3fbedf65e9

1
src/main/scala/Configs.scala
View File

@ -203,6 +203,7 @@ class BaseConfig extends Config (
case UseVM => true
case UseUser => true
case UseDebug => true
case NBreakpoints => 1
case UsePerfCounters => true
case FastLoadWord => true
case FastLoadByte => false

2
src/main/scala/Testing.scala
View File

@ -109,7 +109,7 @@ object DefaultTestSuites {
val rv32siNames = LinkedHashSet("csr", "ma_fetch", "scall", "sbreak", "wfi")
val rv32si = new AssemblyTestSuite("rv32si", "rv32si", rv32siNames)(_)
val rv32miNames = LinkedHashSet("csr", "mcsr", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
val rv32miNames = LinkedHashSet("breakpoint", "csr", "mcsr", "dirty", "illegal", "ma_addr", "ma_fetch", "sbreak", "scall")
val rv32mi = new AssemblyTestSuite("rv32mi", "rv32mi", rv32miNames)(_)
val rv32u = List(rv32ui, rv32um)

2
uncore

Submodule uncore updated: 2929d5384c...7aa159d223