Disable MMIO by default to avoid disconnected nets
This commit is contained in:
2
chisel3
2
chisel3
Submodule chisel3 updated: 0ad47ff929...3ae577bc71
2
firrtl
2
firrtl
Submodule firrtl updated: 592ee2fbc5...a73efa2f67
@ -215,6 +215,7 @@ class DefaultConfig extends Config (
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true
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}
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case NExtInterrupts => 2
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case NExtMMIOChannels => 0
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case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), site(NExtInterrupts))
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case FDivSqrt => true
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case SFMALatency => 2
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@ -19,6 +19,8 @@ case object NBanksPerMemoryChannel extends Field[Int]
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case object BankIdLSB extends Field[Int]
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/** Number of outstanding memory requests */
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case object NOutstandingMemReqsPerChannel extends Field[Int]
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/** Number of exteral MMIO ports */
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case object NExtMMIOChannels extends Field[Int]
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/** Whether to divide HTIF clock */
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case object UseHtifClockDiv extends Field[Boolean]
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/** Function for building some kind of coherence manager agent */
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@ -77,8 +79,8 @@ class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
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class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
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val mem = Vec(nMemChannels, new NastiIO)
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val mmio = new NastiIO
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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val mmio = Vec(p(NExtMMIOChannels), new NastiIO)
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}
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object TopUtils {
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@ -142,13 +144,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
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uncore.io.interrupts <> io.interrupts
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io.mmio <> uncore.io.mmio
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io.mem.zip(uncore.io.mem).foreach { case (outer, inner) =>
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outer <> inner
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// Memory cache type should be normal non-cacheable bufferable
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// TODO why is this happening here? Would 0000 (device) be OK instead?
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outer.ar.bits.cache := UInt("b0011")
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outer.aw.bits.cache := UInt("b0011")
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}
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io.mem <> uncore.io.mem
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}
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/** Wrapper around everything that isn't a Tile.
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@ -164,7 +160,7 @@ class Uncore(implicit val p: Parameters) extends Module
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val tiles_cached = Vec(nCachedTilePorts, new ClientTileLinkIO).flip
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val tiles_uncached = Vec(nUncachedTilePorts, new ClientUncachedTileLinkIO).flip
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val prci = Vec(nTiles, new PRCITileIO).asOutput
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val mmio = new NastiIO
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val mmio = Vec(p(NExtMMIOChannels), new NastiIO)
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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}
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@ -241,7 +237,12 @@ class Uncore(implicit val p: Parameters) extends Module
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val debugModuleAddr = ioAddrHashMap("int:debug")
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debugModule.io <> mmioNetwork.io.out(debugModuleAddr.port)
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TopUtils.connectTilelinkNasti(io.mmio, mmioNetwork.io.out(ioAddrHashMap("ext").port))
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val mmioEndpoint = p(NExtMMIOChannels) match {
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case 0 => Module(new NastiErrorSlave).io
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case 1 => io.mmio(0)
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// The memory map presently has only one external I/O region
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}
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TopUtils.connectTilelinkNasti(mmioEndpoint, mmioNetwork.io.out(ioAddrHashMap("ext").port))
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}
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}
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@ -313,6 +314,11 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
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icPort <> narrow.io.out
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}
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for ((nasti, tl) <- io.mem zip mem_ic.io.out)
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for ((nasti, tl) <- io.mem zip mem_ic.io.out) {
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TopUtils.connectTilelinkNasti(nasti, tl)(outermostTLParams)
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// Memory cache type should be normal non-cacheable bufferable
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// TODO why is this happening here? Would 0000 (device) be OK instead?
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nasti.ar.bits.cache := UInt("b0011")
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nasti.aw.bits.cache := UInt("b0011")
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}
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}
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@ -180,6 +180,7 @@ object TestBenchGeneration extends FileSystemUtilities {
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.io_mem_${i}_w_valid (w_valid_delay_$i),
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.io_mem_${i}_w_ready (w_ready_delay_$i),
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.io_mem_${i}_w_bits_id (),
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.io_mem_${i}_w_bits_strb (w_strb_delay_$i),
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.io_mem_${i}_w_bits_data (w_data_delay_$i),
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.io_mem_${i}_w_bits_last (w_last_delay_$i),
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2
uncore
2
uncore
Submodule uncore updated: 36d6a15155...cf7534a536
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