riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Stub out debug module, rather than leaving it floating

Browse Source
This commit is contained in:
Andrew Waterman 2016-04-30 22:36:06 -07:00
parent 46bbbba5e6
commit c4d2d29e80
3 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
riscv-tools

@ -1 +1 @@
Subproject commit 40a956a7a5335c051416a69eed7d28936b8d967a
Subproject commit b8fe37d17fe4c5be14af6f4975056cdce81691d7

2
rocket

@ -1 +1 @@
Subproject commit 8869c1a44aa91c303eb5ea2bf880e4d74806fce7
Subproject commit 2b5831d9226258f15d28d16135da464f30aac603

4
src/main/scala/RocketChip.scala
View File

@ -218,6 +218,10 @@ class Uncore(implicit val p: Parameters) extends Module
val bootROMAddr = ioAddrHashMap("int:bootrom")
bootROM.io <> mmioNetwork.io.out(bootROMAddr.port)
val debugModule = Module(new ROMSlave(Seq())) // TODO
val debugModuleAddr = ioAddrHashMap("int:debug")
debugModule.io <> mmioNetwork.io.out(debugModuleAddr.port)
TopUtils.connectTilelinkNasti(io.mmio, mmioNetwork.io.out(ioAddrHashMap("ext").port))
}
}