riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman 7380c9fe60 aggressively clock gate int and fp datapaths 2012-11-04 16:40:14 -08:00
Andrew Waterman bd2d61de03 use 8T SRAM for I$; gate clock more aggressively 2012-11-04 16:39:25 -08:00
Andrew Waterman fedee6c67d add generic error correcting codes 2012-10-30 01:03:47 -07:00
Andrew Waterman 5773cbb68a rejigger htif to use UncoreConfiguration 2012-10-18 17:26:03 -07:00
Andrew Waterman b9a2af697d turn off HAVE_VEC as it's currently broken 
the new I$/frontend needs to be integrated
 2012-10-16 07:38:19 -07:00
Andrew Waterman 0a640f2cc6 make DecodeLogic deterministic (hopefully) 2012-10-16 04:51:21 -07:00
Andrew Waterman 5821900329 don't refetch from I$ if on same 16B block 2012-10-16 02:24:38 -07:00
Andrew Waterman b955985b38 improve divider QoR 2012-10-16 02:24:38 -07:00
Andrew Waterman 197154c485 use BTB for JALR 2012-10-16 02:24:37 -07:00
Andrew Waterman fc648d13a1 remove old Mux1H; add implicit conversions 2012-10-16 02:24:37 -07:00
Andrew Waterman 661f8e635b merge I$, ITLB, BTB into Frontend 2012-10-16 02:24:37 -07:00
Andrew Waterman fcd69dba98 add optional early-out to mul/div 2012-10-16 02:24:37 -07:00
Andrew Waterman 27ddff1adb simplify and improve multiplier 2012-10-16 02:24:37 -07:00
Andrew Waterman ed8cc4a1cf eliminate D$ probe->WB critical path 2012-10-04 09:05:14 -07:00
Andrew Waterman 897a4e349b fix some LLC control bugs 2012-08-06 17:10:04 -07:00
Andrew Waterman e9c35b4923 ameliorate DTLB kill->rdy critical path 2012-08-06 17:05:05 -07:00
Andrew Waterman b94e6915ab refactor IPIs; use new tohost/fromhost protocol 2012-08-03 19:00:34 -07:00
Andrew Waterman 6510f020c7 fix deadlock in coherence hub 2012-08-03 19:00:03 -07:00
Andrew Waterman e3726c4db0 fix control bug in LLC 
structural hazard on tag ram caused deadlock
 2012-08-03 18:59:37 -07:00
Andrew Waterman def913096e pipeline LLC further 2012-07-31 17:45:14 -07:00
Andrew Waterman 3a8f3e0de5 further pipeline the LLC 2012-07-30 20:12:11 -07:00
Andrew Waterman be4fa936dd fix PriorityEncoderOH bug 2012-07-30 18:28:54 -07:00
Andrew Waterman 130fa95ed6 expand HTIF's PCR register space 2012-07-27 14:52:39 -07:00
Andrew Waterman 9c50621a19 remove chip-specific uncore gunk 2012-07-26 03:26:52 -07:00
Andrew Waterman a5bea4364f memory system bug fixes 2012-07-26 00:05:21 -07:00
Andrew Waterman 177dbdadd9 merge HTIF port and backup memory port 2012-07-25 00:18:02 -07:00
Andrew Waterman a21c355114 fix htif split request/response 2012-07-23 17:15:16 -07:00
Andrew Waterman 938effc053 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Andrew Waterman f42c6afed2 decouple all interfaces between tile and top 
also, add an "incoherent" bit to tilelink to indicate no probes needed
 2012-07-17 22:55:40 -07:00
Andrew Waterman 4e44ed7400 allow back pressure on IPI requests 2012-07-17 22:55:40 -07:00
Andrew Waterman 5035374f36 update to new chisel 2012-07-08 17:59:41 -07:00
Andrew Waterman 4e5f874266 update to new chisel/hwacha 2012-06-08 00:13:14 -07:00
Andrew Waterman 943b6d0616 remove debug println 2012-06-06 02:48:48 -07:00
Andrew Waterman 7f6319047e update to new scala/chisel/Mem 2012-06-06 02:47:22 -07:00
Andrew Waterman faee45bf4c fix setpcr/clearpcr not writing rd 2012-05-21 07:25:35 -07:00
Andrew Waterman a2f6d01c1b add programmable coreid register 2012-05-09 03:09:22 -07:00
Andrew Waterman e0e1cd5d32 add IPIs and an IPI test 
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
 2012-05-08 22:58:00 -07:00
Andrew Waterman b851f1b34c support maximum-MTU HTIF packets 2012-05-03 21:11:43 -07:00
Andrew Waterman 171c87002e reduce HTIF clock divider for now 2012-05-03 04:21:11 -07:00
Andrew Waterman e1f9dc2c1f generalize page table walker 
also, don't instantiate vitlb when !HAVE_VEC
 2012-05-03 02:29:09 -07:00
Andrew Waterman 2d4e5d3813 fix pseudo-LRU verilog generation bug 2012-05-02 19:31:31 -07:00
Andrew Waterman 65ff397122 improved instruction decoding 
it now makes use of don't-cares by performing logic minimization
 2012-05-01 20:16:36 -07:00
Andrew Waterman 4cfa6cd9a8 force Top.main's return type to Unit 2012-05-01 19:55:16 -07:00
Andrew Waterman 5819beed64 use parameterized FP units 2012-05-01 01:25:43 -07:00
Andrew Waterman eafdffe125 simplify page table walker; speed up emulator 2012-05-01 01:24:36 -07:00
Andrew Waterman c13d3e6f88 fix probe tag read-modify-write atomicity violation 2012-04-26 02:29:31 -07:00
Andrew Waterman 66f86a2194 use pseudo-LRU replacement for TLBs 2012-04-26 02:29:30 -07:00
Andrew Waterman a0378c5d2f remove faulting TLB entry after page fault 
this vastly reduces the frequency with which the TLB must be flushed
 2012-04-26 02:29:30 -07:00
Andrew Waterman 6d8fc74378 fix DTLB permissions bug 2012-04-26 02:29:30 -07:00
Andrew Waterman fb4408b150 fix AMO replay/coherence deadlock 2012-04-15 22:56:02 -07:00
Andrew Waterman 724735f13f fix writeback bug 2012-04-13 03:16:48 -07:00
Andrew Waterman 00d934cfac fix coherence bugs in cache 2012-04-12 21:57:37 -07:00
Andrew Waterman c0ec3794bf coherence mostly works now 2012-04-10 02:22:45 -07:00
Andrew Waterman aee9378712 fix coherence bug with multiple probe replies 2012-04-09 21:40:35 -07:00
Andrew Waterman 7f254d9670 refine FP bugfixes 2012-04-01 14:52:33 -07:00
Andrew Waterman a09e8d1c55 remove I$ prefetcher for now 
there's a bug in it, and I don't have time to fix it at the moment.
 2012-03-27 15:43:56 -07:00
Andrew Waterman 452876af37 fence on vvcfg; implement fence.v.g correctly 2012-03-27 14:49:00 -07:00
Andrew Waterman 6bda8674bd no dessert tonight :( 2012-03-26 23:50:09 -07:00
Andrew Waterman e2fe525fb6 remove bug from dessert 2012-03-26 14:18:57 -07:00
Andrew Waterman 5f53cd4ac1 reduce HTIF width 2012-03-25 23:49:59 -07:00
Andrew Waterman ef505de017 reduce HTIF width 2012-03-25 23:49:45 -07:00
Andrew Waterman 31f0b600fd add dessert 2012-03-25 23:03:20 -07:00
Andrew Waterman 1666d3fbd7 loop host.in to host.out during reset 2012-03-25 21:45:10 -07:00
Andrew Waterman f62a02ab54 remove dumb stuff in top.scala 2012-03-25 21:30:01 -07:00
Andrew Waterman 88bf8a4f23 add mem serdes unit 2012-03-25 17:03:58 -07:00
Andrew Waterman 7fa93da4f5 add backup memory port (disabled for now) 2012-03-25 15:49:32 -07:00
Andrew Waterman 86d56ff67b refactor cpu/i$/d$ into Tile (rather than Top) 2012-03-24 16:57:28 -07:00
Andrew Waterman 3a487ac89b improve htif<->pcr interface 2012-03-24 16:57:28 -07:00
Andrew Waterman 54fa6f660d new supervisor mode 2012-03-24 13:03:31 -07:00
Andrew Waterman bd27d0fab2 can now take interrupts on stalled instructions 2012-03-19 01:02:06 -07:00
Andrew Waterman 2ed0be65f9 fix RRArbiter 2012-03-19 00:19:33 -07:00
Andrew Waterman c4a91303fb update vector fence names and encoding 2012-03-18 20:42:38 -07:00
Andrew Waterman a47eeb9571 retime D$ bypass into beginning of EX stage 2012-03-16 18:35:54 -07:00
Andrew Waterman 6c26921766 reduce D$ critical path through page table walker 
costs an extra cycle per page table level to resolve a TLB miss. too bad.
 2012-03-16 18:35:54 -07:00
Andrew Waterman f0157b9e2a fix coherence bug 
popping wrong store dependence queue
 2012-03-16 01:24:07 -07:00
Andrew Waterman cfca2d1411 clean up cache interfaces; avoid reserved keywords 2012-03-16 00:44:16 -07:00
Andrew Waterman 820884c7e6 fix probes for smaller cache sizes 
address bits (pgidx_bits-1,taglsb) were omitted from tag checks.
 2012-03-15 23:08:30 -07:00
Andrew Waterman 4684171ac6 fix fence.i for associative caches 2012-03-15 21:23:21 -07:00
Andrew Waterman 2b0bc8df2b use divided clk for htif. UDPATE YOUR FESVR 
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
 2012-03-15 18:36:51 -07:00
Andrew Waterman 7dde7099d2 use broadcast hub and coherent HTIF 2012-03-14 16:44:35 -07:00
Andrew Waterman ab6c9350db fix minor coherence bugs 2012-03-13 19:10:54 -07:00
Andrew Waterman 1788c34113 parameterize broadcast hub by # of tiles 2012-03-13 17:12:01 -07:00
Andrew Waterman 1492457df5 add probe replies to HTIF 2012-03-13 16:56:47 -07:00
Andrew Waterman b0f798962c add probe unit 2012-03-13 16:43:51 -07:00
Andrew Waterman d76b05bde1 fix way selection on D$ write upgrades 2012-03-13 02:21:02 -07:00
Andrew Waterman fd29e00db0 support non-power-of-2 queue sizes 
need to manually wrap queue pointers.
 2012-03-13 01:58:28 -07:00
Andrew Waterman 8ffdac9526 fix D$ store-upgrade bug 
loads to the same address as stores that cause an upgrade
could return the old value
 2012-03-10 15:50:10 -08:00
Andrew Waterman 4f4b990a4f fix null hub store ack bug 2012-03-10 15:19:12 -08:00
Andrew Waterman 7eb73c325e fix signedness of zero fmul results 
We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0.  Now we
add -0.0 if rs1*rs2 is negative.
 2012-03-10 00:21:51 -08:00
Andrew Waterman e3a68848e0 fix D$ critical paths and fix verilog build 2012-03-09 20:02:51 -08:00
Andrew Waterman 85504f0ddc fix bug in fence.i and improve test 2012-03-09 03:26:05 -08:00
Andrew Waterman 766bac88f8 refactor D$ writebacks and flushes 
MSHRs now arbitrate for writebacks and handle flushes.
 2012-03-09 02:55:46 -08:00
Andrew Waterman ff2e47f380 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Andrew Waterman 5a7c5772a8 clearly distinguish PPN and cache tag 2012-03-07 23:11:17 -08:00
Andrew Waterman 941873bad1 coherence hub fixes 2012-03-07 21:03:44 -08:00
Andrew Waterman c09eeb7fd2 fix D$ next-state logic 
it was using the CPU command from the wrong pipeline stage,
which was a don't-care with ThreeStateIncoherence.
 2012-03-07 01:42:08 -08:00
Andrew Waterman a0c9452b86 change D$ to use FourStateCoherence protocol 
instead of ThreeStateIncoherence.
 2012-03-07 01:26:35 -08:00
Andrew Waterman 6e2610b0ad fix Mux1H for bundles 2012-03-06 23:38:36 -08:00
Andrew Waterman 499c5b4a2e automatically infer MEM_TAG_BITS 2012-03-06 15:49:28 -08:00
Andrew Waterman 6e16b04ada implement transaction finish messages 2012-03-06 15:48:08 -08:00