riscv/rocket-chip
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Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)
339 Commits 1 Branch 0 Tags 13 MiB
Scala 93.1%
C++ 2.1%
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Andrew Waterman 2b0bc8df2b use divided clk for htif. UDPATE YOUR FESVR 
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
2012-03-15 18:36:51 -07:00
rocket/src/main/scala use divided clk for htif. UDPATE YOUR FESVR 2012-03-15 18:36:51 -07:00