remove old Mux1H; add implicit conversions
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661f8e635b
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fc648d13a1
@ -28,34 +28,29 @@ class rocketDpathBTB(entries: Int) extends Component
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val hit = Bool()
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val update = Bool()
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var update_reduction = Bool(false)
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val mux = (new Mux1H(entries)) { Bits(width = VADDR_BITS) }
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val hits = Vec(entries) { Bool() }
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val updates = Vec(entries) { Bool() }
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val targets = Vec(entries) { Reg() { UFix() } }
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val anyUpdate = updates.toBits.orR
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for (i <- 0 until entries) {
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val tag = Reg() { UFix() }
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val target = Reg() { UFix() }
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val valid = Reg(resetVal = Bool(false))
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val my_hit = valid && tag === io.current_pc
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val my_update = valid && tag === io.correct_pc
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hits(i) := valid && tag === io.current_pc
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updates(i) := valid && tag === io.correct_pc
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when (io.wen && (my_update || !update && UFix(i) === repl_way)) {
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when (io.wen && (updates(i) || !anyUpdate && UFix(i) === repl_way)) {
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valid := Bool(false)
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when (!io.clr) {
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valid := Bool(true)
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tag := io.correct_pc
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target := io.correct_target
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targets(i) := io.correct_target
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}
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}
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hit_reduction = hit_reduction || my_hit
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update_reduction = update_reduction || my_update
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mux.io.sel(i) := my_hit
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mux.io.in(i) := target
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}
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hit := hit_reduction
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update := update_reduction
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io.hit := hit
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io.target := mux.io.out.toUFix
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io.hit := hits.toBits.orR
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io.target := Mux1H(hits, targets)
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}
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class ioDpathPCR extends Bundle()
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@ -189,11 +189,10 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
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io.mem.probe_rep_data.valid := Bool(false)
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io.mem.incoherent := Bool(true)
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val pcr_mux = (new Mux1H(ncores)) { Bits(width = 64) }
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val pcrReadData = Vec(ncores) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } }
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for (i <- 0 until ncores) {
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val my_reset = Reg(resetVal = Bool(true))
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val my_ipi = Reg(resetVal = Bool(false))
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val rdata = Reg() { Bits() }
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val cpu = io.cpu(i)
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val me = pcr_coreid === UFix(i)
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@ -221,25 +220,22 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
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when (cmd === cmd_writecr) {
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my_reset := pcr_wdata(0)
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}
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rdata := my_reset.toBits
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pcrReadData(i) := my_reset.toBits
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state := state_tx
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}
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cpu.pcr_rep.ready := Bool(true)
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when (cpu.pcr_rep.valid) {
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rdata := cpu.pcr_rep.bits
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pcrReadData(i) := cpu.pcr_rep.bits
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state := state_tx
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}
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pcr_mux.io.sel(i) := me
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pcr_mux.io.in(i) := rdata
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}
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val tx_cmd = Mux(nack, cmd_nack, cmd_ack)
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val tx_cmd_ext = Cat(Bits(0, 4-tx_cmd.getWidth), tx_cmd)
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val tx_header = Cat(addr, seqno, tx_size, tx_cmd_ext)
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val tx_data = Mux(tx_word_count === UFix(0), tx_header,
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Mux(cmd === cmd_readcr || cmd === cmd_writecr, pcr_mux.io.out,
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Mux(cmd === cmd_readcr || cmd === cmd_writecr, pcrReadData(pcr_coreid),
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packet_ram(packet_ram_raddr)))
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io.host.in.ready := state === state_rx
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@ -325,9 +325,10 @@ class MSHRFile(co: CoherencePolicy) extends Component {
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val sdq = Mem(NSDQ) { io.req.bits.data.clone }
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when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data }
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val tag_mux = (new Mux1H(NMSHR)){ Bits(width = TAG_BITS) }
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val wb_probe_mux = (new Mux1H(NMSHR)) { new WritebackReq }
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val mem_resp_mux = (new Mux1H(NMSHR)){ new DataArrayReq }
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val idxMatch = Vec(NMSHR) { Bool() }
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val tagList = Vec(NMSHR) { Bits() }
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val wbTagList = Vec(NMSHR) { Bits() }
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val memRespMux = Vec(NMSHR) { new DataArrayReq }
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val meta_req_arb = (new Arbiter(NMSHR)) { new MetaArrayReq() }
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val mem_req_arb = (new Arbiter(NMSHR)) { new TransactionInit }
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val mem_finish_arb = (new Arbiter(NMSHR)) { new TransactionFinish }
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@ -335,8 +336,8 @@ class MSHRFile(co: CoherencePolicy) extends Component {
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val replay_arb = (new Arbiter(NMSHR)) { new Replay() }
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val alloc_arb = (new Arbiter(NMSHR)) { Bool() }
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val tag_match = tag_mux.io.out === io.req.bits.tag
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val wb_probe_match = wb_probe_mux.io.out.tag === io.req.bits.tag
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val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.tag
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val wb_probe_match = Mux1H(idxMatch, wbTagList) === io.req.bits.tag
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var idx_match = Bool(false)
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var pri_rdy = Bool(false)
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@ -348,10 +349,9 @@ class MSHRFile(co: CoherencePolicy) extends Component {
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for (i <- 0 to NMSHR-1) {
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val mshr = new MSHR(i, co)
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tag_mux.io.sel(i) := mshr.io.idx_match
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tag_mux.io.in(i) := mshr.io.tag
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wb_probe_mux.io.sel(i) := mshr.io.idx_match
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wb_probe_mux.io.in(i) := mshr.io.wb_req.bits
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idxMatch(i) := mshr.io.idx_match
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tagList(i) := mshr.io.tag
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wbTagList(i) := mshr.io.wb_req.bits.tag
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alloc_arb.io.in(i).valid := mshr.io.req_pri_rdy
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mshr.io.req_pri_val := alloc_arb.io.in(i).ready
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@ -371,10 +371,9 @@ class MSHRFile(co: CoherencePolicy) extends Component {
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mshr.io.mem_abort <> io.mem_abort
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mshr.io.mem_rep <> io.mem_rep
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mem_resp_mux.io.sel(i) := UFix(i) === io.mem_rep.bits.tile_xact_id
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mem_resp_mux.io.in(i).idx := mshr.io.idx
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mem_resp_mux.io.in(i).offset := mshr.io.refill_count
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mem_resp_mux.io.in(i).way_en := mshr.io.way_oh
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memRespMux(i).idx := mshr.io.idx
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memRespMux(i).offset := mshr.io.refill_count
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memRespMux(i).way_en := mshr.io.way_oh
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pri_rdy = pri_rdy || mshr.io.req_pri_rdy
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sec_rdy = sec_rdy || mshr.io.req_sec_rdy
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@ -393,9 +392,10 @@ class MSHRFile(co: CoherencePolicy) extends Component {
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io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
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io.secondary_miss := idx_match
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io.mem_resp_idx := mem_resp_mux.io.out.idx
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io.mem_resp_offset := mem_resp_mux.io.out.offset
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io.mem_resp_way_oh := mem_resp_mux.io.out.way_en
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val memResp = memRespMux(io.mem_rep.bits.tile_xact_id)
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io.mem_resp_idx := memResp.idx
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io.mem_resp_offset := memResp.offset
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io.mem_resp_way_oh := memResp.way_en
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io.fence_rdy := !fence
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io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match)
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@ -4,13 +4,9 @@ import Chisel._
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import Node._
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import scala.math._
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class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
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object Util
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{
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val io = new Bundle {
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val sel = Vec(n) { Bool(dir = INPUT) }
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val in = Vec(n) { gen }.asInput
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val out = gen.asOutput
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}
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io.out := Mux1H(io.sel, io.in)
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implicit def intToUFix(x: Int): UFix = UFix(x)
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implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false
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implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0
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}
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