use parameterized FP units
This commit is contained in:
Andrew Waterman
parent
eafdffe125
commit
5819beed64
@ -195,57 +195,48 @@ class rocketFPIntUnit extends Component
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val exc = Bits(5, OUTPUT)
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}
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val unrec_s = new hardfloat.recodedFloat32ToFloat32
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val unrec_d = new hardfloat.recodedFloat64ToFloat64
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unrec_s.io.in := io.in1
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unrec_d.io.in := io.in1
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val unrec_s = hardfloat.recodedFloatNToFloatN(io.in1, 23, 9)
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val unrec_d = hardfloat.recodedFloatNToFloatN(io.in1, 52, 12)
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io.store_data := Mux(io.single, Cat(unrec_s.io.out, unrec_s.io.out), unrec_d.io.out)
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io.store_data := Mux(io.single, Cat(unrec_s, unrec_s), unrec_d)
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val scmp = new hardfloat.recodedFloat32Compare
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val scmp = new hardfloat.recodedFloatNCompare(23, 9)
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scmp.io.a := io.in1
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scmp.io.b := io.in2
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val scmp_out = (io.cmd & Cat(scmp.io.a_lt_b, scmp.io.a_eq_b)).orR
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val scmp_exc = (io.cmd & Cat(scmp.io.a_lt_b_invalid, scmp.io.a_eq_b_invalid)).orR << UFix(4)
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val s2i = new hardfloat.recodedFloat32ToAny
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s2i.io.in := io.in1
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s2i.io.roundingMode := io.rm
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s2i.io.typeOp := ~io.cmd(1,0)
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val dcmp = new hardfloat.recodedFloat64Compare
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val dcmp = new hardfloat.recodedFloatNCompare(52, 12)
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dcmp.io.a := io.in1
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dcmp.io.b := io.in2
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val dcmp_out = (io.cmd & Cat(dcmp.io.a_lt_b, dcmp.io.a_eq_b)).orR
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val dcmp_exc = (io.cmd & Cat(dcmp.io.a_lt_b_invalid, dcmp.io.a_eq_b_invalid)).orR << UFix(4)
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val d2i = new hardfloat.recodedFloat64ToAny
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d2i.io.in := io.in1
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d2i.io.roundingMode := io.rm
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d2i.io.typeOp := ~io.cmd(1,0)
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val s2i = hardfloat.recodedFloatNToAny(io.in1, io.rm, ~io.cmd(1,0), 23, 9, 64)
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val d2i = hardfloat.recodedFloatNToAny(io.in1, io.rm, ~io.cmd(1,0), 52, 12, 64)
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// output muxing
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val (out_s, exc_s) = (Wire() { Bits() }, Wire() { Bits() })
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out_s := Cat(Fill(32, unrec_s.io.out(31)), unrec_s.io.out)
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out_s := Cat(Fill(32, unrec_s(31)), unrec_s)
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exc_s := Bits(0)
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val (out_d, exc_d) = (Wire() { Bits() }, Wire() { Bits() })
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out_d := unrec_d.io.out
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out_d := unrec_d
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exc_d := Bits(0)
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when (io.cmd === FCMD_MTFSR || io.cmd === FCMD_MFFSR) {
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out_s := io.fsr
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}
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when (io.cmd === FCMD_CVT_W_FMT || io.cmd === FCMD_CVT_WU_FMT) {
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out_s := Cat(Fill(32, s2i.io.out(31)), s2i.io.out(31,0))
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exc_s := s2i.io.exceptionFlags
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out_d := Cat(Fill(32, d2i.io.out(31)), d2i.io.out(31,0))
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exc_d := d2i.io.exceptionFlags
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out_s := Cat(Fill(32, s2i._1(31)), s2i._1(31,0))
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exc_s := s2i._2
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out_d := Cat(Fill(32, d2i._1(31)), d2i._1(31,0))
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exc_d := d2i._2
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}
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when (io.cmd === FCMD_CVT_L_FMT || io.cmd === FCMD_CVT_LU_FMT) {
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out_s := s2i.io.out
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exc_s := s2i.io.exceptionFlags
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out_d := d2i.io.out
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exc_d := d2i.io.exceptionFlags
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out_s := s2i._1
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exc_s := s2i._2
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out_d := d2i._1
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exc_d := d2i._2
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}
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when (io.cmd === FCMD_EQ || io.cmd === FCMD_LT || io.cmd === FCMD_LE) {
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out_s := scmp_out
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@ -277,21 +268,8 @@ class rocketFPUFastPipe extends Component
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val exc_d = Bits(5, OUTPUT)
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}
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// int->fp units
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val rec_s = new hardfloat.float32ToRecodedFloat32
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val rec_d = new hardfloat.float64ToRecodedFloat64
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rec_s.io.in := io.fromint
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rec_d.io.in := io.fromint
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val i2s = new hardfloat.anyToRecodedFloat32
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i2s.io.in := io.fromint
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i2s.io.roundingMode := io.rm
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i2s.io.typeOp := ~io.cmd(1,0)
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val i2d = new hardfloat.anyToRecodedFloat64
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i2d.io.in := io.fromint
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i2d.io.roundingMode := io.rm
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i2d.io.typeOp := ~io.cmd(1,0)
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val i2s = hardfloat.anyToRecodedFloatN(io.fromint, io.rm, ~io.cmd(1,0), 23, 9, 64)
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val i2d = hardfloat.anyToRecodedFloatN(io.fromint, io.rm, ~io.cmd(1,0), 52, 12, 64)
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// fp->fp units
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val sign_s = Mux(io.cmd === FCMD_SGNJ, io.in2(32),
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@ -303,12 +281,8 @@ class rocketFPUFastPipe extends Component
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val fsgnj = Cat(Mux(io.single, io.in1(64), sign_d), io.in1(63,33),
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Mux(io.single, sign_s, io.in1(32)), io.in1(31,0))
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val s2d = new hardfloat.recodedFloat32ToRecodedFloat64
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s2d.io.in := io.in1
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val d2s = new hardfloat.recodedFloat64ToRecodedFloat32
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d2s.io.in := io.in1
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d2s.io.roundingMode := io.rm
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val s2d = hardfloat.recodedFloatNToRecodedFloatM(io.in1, io.rm, 23, 9, 52, 12)
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val d2s = hardfloat.recodedFloatNToRecodedFloatM(io.in1, io.rm, 52, 12, 23, 9)
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val isnan1 = Mux(io.single, io.in1(31,29) === Bits("b111"), io.in1(63,61) === Bits("b111"))
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val isnan2 = Mux(io.single, io.in2(31,29) === Bits("b111"), io.in2(63,61) === Bits("b111"))
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@ -321,10 +295,10 @@ class rocketFPUFastPipe extends Component
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// output muxing
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val (out_s, exc_s) = (Wire() { Bits() }, Wire() { Bits() })
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out_s := Reg(rec_s.io.out)
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out_s := Reg(hardfloat.floatNToRecodedFloatN(io.fromint, 23, 9))
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exc_s := Bits(0)
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val (out_d, exc_d) = (Wire() { Bits() }, Wire() { Bits() })
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out_d := Reg(rec_d.io.out)
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out_d := Reg(hardfloat.floatNToRecodedFloatN(io.fromint, 52, 12))
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exc_d := Bits(0)
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val r_cmd = Reg(io.cmd)
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@ -346,17 +320,17 @@ class rocketFPUFastPipe extends Component
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exc_d := r_minmax_exc
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}
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when (r_cmd === FCMD_CVT_FMT_S || r_cmd === FCMD_CVT_FMT_D) {
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out_s := Reg(d2s.io.out)
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exc_s := Reg(d2s.io.exceptionFlags)
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out_d := Reg(s2d.io.out)
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exc_d := Reg(s2d.io.exceptionFlags)
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out_s := Reg(d2s._1)
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exc_s := Reg(d2s._2)
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out_d := Reg(s2d._1)
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exc_d := Reg(s2d._2)
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}
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when (r_cmd === FCMD_CVT_FMT_W || r_cmd === FCMD_CVT_FMT_WU ||
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r_cmd === FCMD_CVT_FMT_L || r_cmd === FCMD_CVT_FMT_LU) {
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out_s := Reg(i2s.io.out)
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exc_s := Reg(i2s.io.exceptionFlags)
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out_d := Reg(i2d.io.out)
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exc_d := Reg(i2d.io.exceptionFlags)
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out_s := Reg(i2s._1)
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exc_s := Reg(i2s._2)
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out_d := Reg(i2d._1)
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exc_d := Reg(i2d._2)
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}
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io.out_s := out_s
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@ -401,7 +375,7 @@ class rocketFPUSFMAPipe(latency: Int) extends Component
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in3 := Mux(cmd_fma, io.in3, Mux(cmd_addsub, io.in2, zero))
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}
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val fma = new hardfloat.mulAddSubRecodedFloat32_1
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val fma = new hardfloat.mulAddSubRecodedFloatN(23, 9)
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fma.io.op := cmd
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fma.io.roundingMode := rm
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fma.io.a := in1
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@ -437,7 +411,7 @@ class rocketFPUDFMAPipe(latency: Int) extends Component
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in3 := Mux(cmd_fma, io.in3, Mux(cmd_addsub, io.in2, zero))
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}
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val fma = new hardfloat.mulAddSubRecodedFloat64_1
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val fma = new hardfloat.mulAddSubRecodedFloatN(52, 12)
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fma.io.op := cmd
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fma.io.roundingMode := rm
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fma.io.a := in1
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@ -483,12 +457,10 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
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load_wb_data := io.dpath.dmem_resp_data
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load_wb_tag := io.dpath.dmem_resp_tag
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}
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val rec_s = new hardfloat.float32ToRecodedFloat32
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val rec_d = new hardfloat.float64ToRecodedFloat64
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rec_s.io.in := load_wb_data
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rec_d.io.in := load_wb_data
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val rec_s = hardfloat.floatNToRecodedFloatN(load_wb_data, 23, 9)
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val rec_d = hardfloat.floatNToRecodedFloatN(load_wb_data, 52, 12)
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val sp_msbs = Fill(32, UFix(1,1))
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val load_wb_data_recoded = Mux(load_wb_single, Cat(sp_msbs, rec_s.io.out), rec_d.io.out)
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val load_wb_data_recoded = Mux(load_wb_single, Cat(sp_msbs, rec_s), rec_d)
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val fsr_rm = Reg() { Bits(width = 3) }
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val fsr_exc = Reg() { Bits(width = 5) }
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