rejigger htif to use UncoreConfiguration

rocket/src/main/scala/cpu.scala

@@ -7,7 +7,7 @@ import hwacha._
 
 class ioRocket(implicit conf: RocketConfiguration) extends Bundle
 {
-  val host    = new ioHTIF
+  val host    = new ioHTIF(conf.ntiles)
   val imem    = new IOCPUFrontend
   val vimem   = new IOCPUFrontend
   val dmem    = new ioHellaCache

rocket/src/main/scala/dpath.scala

@@ -8,7 +8,7 @@ import hwacha._
 
 class ioDpathAll(implicit conf: RocketConfiguration) extends Bundle
 {
-  val host  = new ioHTIF
+  val host  = new ioHTIF(conf.ntiles)
   val ctrl  = new ioCtrlDpath().flip
   val dmem = new ioHellaCache
   val dtlb = new ioDTLB_CPU_req_bundle().asOutput()

rocket/src/main/scala/dpath_util.scala

@@ -55,7 +55,7 @@ class rocketDpathBTB(entries: Int) extends Component
 
 class ioDpathPCR(implicit conf: RocketConfiguration) extends Bundle
 {
-  val host  = new ioHTIF
+  val host  = new ioHTIF(conf.ntiles)
   val r     = new ioReadPort();
   val w     = new ioWritePort();
   

rocket/src/main/scala/htif.scala

@@ -10,8 +10,10 @@ class ioDebug extends Bundle
   val error_mode  = Bool(OUTPUT);
 }
 
-class ioHost(w: Int) extends Bundle
+class ioHost(val w: Int) extends Bundle
 {
+  val clk = Bool(OUTPUT)
+  val clk_edge = Bool(OUTPUT)
   val in = new FIFOIO()(Bits(width = w)).flip
   val out = new FIFOIO()(Bits(width = w))
 }
@@ -23,21 +25,21 @@ class PCRReq extends Bundle
   val data = Bits(width = 64)
 }
 
-class ioHTIF(implicit conf: RocketConfiguration) extends Bundle
+class ioHTIF(ntiles: Int) extends Bundle
 {
   val reset = Bool(INPUT)
   val debug = new ioDebug
   val pcr_req = (new FIFOIO) { new PCRReq }.flip
   val pcr_rep = (new FIFOIO) { Bits(width = 64) }
-  val ipi_req = (new FIFOIO) { Bits(width = log2Up(conf.ntiles)) }
+  val ipi_req = (new FIFOIO) { Bits(width = log2Up(ntiles)) }
   val ipi_rep = (new FIFOIO) { Bool() }.flip
 }
 
-class rocketHTIF(w: Int)(implicit conf: RocketConfiguration) extends Component
+class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component
 {
   val io = new Bundle {
     val host = new ioHost(w)
-    val cpu = Vec(conf.ntiles) { new ioHTIF().flip }
+    val cpu = Vec(conf.ntiles) { new ioHTIF(conf.ntiles).flip }
     val mem = new ioTileLink
   }
 
@@ -178,7 +180,8 @@ class rocketHTIF(w: Int)(implicit conf: RocketConfiguration) extends Component
   }
   x_init.io.enq.valid := state === state_mem_req
   val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3)
-  x_init.io.enq.bits := Mux(cmd === cmd_writemem, conf.co.getUncachedWriteTransactionInit(init_addr, UFix(0)), conf.co.getUncachedReadTransactionInit(init_addr, UFix(0)))
+  val co = conf.co.asInstanceOf[CoherencePolicyWithUncached]
+  x_init.io.enq.bits := Mux(cmd === cmd_writemem, co.getUncachedWriteTransactionInit(init_addr, UFix(0)), co.getUncachedReadTransactionInit(init_addr, UFix(0)))
   io.mem.xact_init <> x_init.io.deq
   io.mem.xact_init_data.valid:= state === state_mem_wdata
   io.mem.xact_init_data.bits.data := mem_req_data

rocket/src/main/scala/tile.scala

@@ -9,7 +9,7 @@ class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends
 {
   val io = new Bundle {
     val tilelink = new ioTileLink
-    val host = new ioHTIF
+    val host = new ioHTIF(conf.ntiles)
   }
   
   val cpu       = new rocketProc

rocket/src/main/scala/top.scala

@@ -25,16 +25,16 @@ class Top extends Component
               else new MICoherence
             }
   implicit val rconf = RocketConfiguration(NTILES, co)
-  implicit val uconf = UncoreConfiguration(NTILES+1, log2Up(NTILES)+1)
+  implicit val uconf = UncoreConfiguration(NTILES+1, log2Up(NTILES)+1, co)
 
   val io = new Bundle  {
     val debug   = new ioDebug
-    val host    = new ioHost(HTIF_WIDTH)
+    val host    = new ioHost(16)
     val mem     = new ioMemPipe
   }
 
-  val htif = new rocketHTIF(HTIF_WIDTH)
-  val hub = new CoherenceHubBroadcast(co)
+  val htif = new rocketHTIF(io.host.w)
+  val hub = new CoherenceHubBroadcast
   hub.io.tiles(NTILES) <> htif.io.mem
   io.host <> htif.io.host