reduce HTIF clock divider for now
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parent
e1f9dc2c1f
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@ -3,7 +3,7 @@ package rocket
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import Chisel._
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import Constants._
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class slowIO[T <: Data](divisor: Int, hold_cycles: Int)(data: => T) extends Component
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class slowIO[T <: Data](val divisor: Int, hold_cycles_in: Int = -1)(data: => T) extends Component
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{
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val io = new Bundle {
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val out_fast = new ioDecoupled()(data).flip
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@ -15,8 +15,9 @@ class slowIO[T <: Data](divisor: Int, hold_cycles: Int)(data: => T) extends Comp
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val clk_slow = Bool(OUTPUT)
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}
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val hold_cycles = if (hold_cycles_in == -1) divisor/4 else hold_cycles_in
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require((divisor & (divisor-1)) == 0)
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require(hold_cycles < divisor/2 && hold_cycles >= 2)
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require(hold_cycles < divisor/2 && hold_cycles >= 1)
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val cnt = Reg() { UFix(width = log2up(divisor)) }
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cnt := cnt + UFix(1)
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@ -16,7 +16,7 @@ class ioTop(htif_width: Int) extends Bundle {
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class Top extends Component
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{
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val clkdiv = 32
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val clkdiv = 8
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val htif_width = 8
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val io = new ioTop(htif_width)
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@ -53,7 +53,7 @@ class Top extends Component
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hub.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits)
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// pad out the HTIF using a divided clock
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val hio = (new slowIO(clkdiv, 4)) { Bits(width = htif_width) }
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val hio = (new slowIO(clkdiv)) { Bits(width = htif_width) }
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htif.io.host.out <> hio.io.out_fast
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io.host.out <> hio.io.out_slow
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htif.io.host.in <> hio.io.in_fast
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@ -61,7 +61,7 @@ class Top extends Component
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io.host_clk := hio.io.clk_slow
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// pad out the backup memory link with the HTIF divided clk
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val mio = (new slowIO(clkdiv, 4)) { Bits(width = MEM_BACKUP_WIDTH) }
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val mio = (new slowIO(clkdiv)) { Bits(width = MEM_BACKUP_WIDTH) }
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mem_serdes.io.narrow.req <> mio.io.out_fast
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io.mem_backup.req <> mio.io.out_slow
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mem_serdes.io.narrow.resp.valid := mio.io.in_fast.valid
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