riscv/rocket-chip
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refactor cpu/i$/d$ into Tile (rather than Top)

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This commit is contained in:
Andrew Waterman 2012-03-24 16:56:59 -07:00
parent 3a487ac89b
commit 86d56ff67b
7 changed files with 59 additions and 47 deletions
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2
rocket/src/main/scala/consts.scala
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@ -7,7 +7,7 @@ object Constants
{
val HAVE_RVC = false
val HAVE_FPU = true
val HAVE_VEC = true
val HAVE_VEC = false
val BR_N = UFix(0, 4);
val BR_EQ = UFix(1, 4);

7
rocket/src/main/scala/cpu.scala
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@ -5,14 +5,8 @@ import Node._;
import Constants._;
import hwacha._
class ioDebug(view: List[String] = null) extends Bundle(view)
{
val error_mode = Bool(OUTPUT);
}
class ioRocket extends Bundle()
{
val debug = new ioDebug();
val host = new ioHTIF();
val imem = new ioImem().flip
val vimem = new ioImem().flip
@ -107,7 +101,6 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
ctrl.io.dpath <> dpath.io.ctrl;
dpath.io.host <> io.host;
dpath.io.debug <> io.debug;
// FIXME: try to make this more compact

2
rocket/src/main/scala/dpath.scala
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@ -17,7 +17,6 @@ class ioDpathAll extends Bundle()
{
val host = new ioHTIF();
val ctrl = new ioCtrlDpath().flip
val debug = new ioDebug();
val dmem = new ioDmem(List("req_idx", "req_tag", "req_data", "resp_val", "resp_miss", "resp_replay", "resp_type", "resp_tag", "resp_data", "resp_data_subword")).flip
val dtlb = new ioDTLB_CPU_req_bundle().asOutput()
val imem = new ioDpathImem();
@ -291,7 +290,6 @@ class rocketDpath extends Component
io.ctrl.status := pcr.io.status;
io.ptbr := pcr.io.ptbr;
io.ptbr_wen := pcr.io.ptbr_wen;
io.debug.error_mode := pcr.io.debug.error_mode;
// branch resolution logic
io.ctrl.br_eq := (ex_rs1 === ex_rs2)

3
rocket/src/main/scala/dpath_util.scala
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@ -60,7 +60,6 @@ class rocketDpathBTB(entries: Int) extends Component
class ioDpathPCR extends Bundle()
{
val host = new ioHTIF()
val debug = new ioDebug(List("error_mode", "log_control"));
val r = new ioReadPort();
val w = new ioWritePort();
@ -133,7 +132,7 @@ class rocketDpathPCR extends Component
io.status := Cat(reg_status_im, Bits(0,7), reg_status_vm, reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et);
io.evec := Mux(io.exception, reg_ebase, reg_epc)
io.ptbr := reg_ptbr;
io.debug.error_mode := reg_error_mode;
io.host.debug.error_mode := reg_error_mode;
io.r.data := rdata;
io.vecbank := reg_vecbank

6
rocket/src/main/scala/htif.scala
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@ -4,6 +4,11 @@ import Chisel._
import Node._;
import Constants._;
class ioDebug(view: List[String] = null) extends Bundle(view)
{
val error_mode = Bool(OUTPUT);
}
class ioHost(w: Int, view: List[String] = null) extends Bundle(view)
{
val in = new ioDecoupled()(Bits(width = w)).flip
@ -20,6 +25,7 @@ class PCRReq extends Bundle
class ioHTIF extends Bundle
{
val reset = Bool(INPUT)
val debug = new ioDebug
val pcr_req = (new ioDecoupled) { new PCRReq }.flip
val pcr_rep = (new ioPipe) { Bits(width = 64) }
}

45
rocket/src/main/scala/tile.scala Normal file
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@ -0,0 +1,45 @@
package rocket
import Chisel._
import Node._
import Constants._
class Tile extends Component
{
val io = new Bundle {
val tilelink = new ioTileLink
val host = new ioHTIF
}
val cpu = new rocketProc(resetSignal = io.host.reset)
val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB)
val icache_pf = new rocketIPrefetcher
val dcache = new HellaCacheUniproc
val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0))
arbiter.io.requestor(0) <> dcache.io.mem
arbiter.io.requestor(1) <> icache_pf.io.mem
io.tilelink.xact_init <> Queue(arbiter.io.mem.xact_init)
io.tilelink.xact_init_data <> Queue(dcache.io.mem.xact_init_data)
arbiter.io.mem.xact_abort <> Queue(io.tilelink.xact_abort)
arbiter.io.mem.xact_rep <> Pipe(io.tilelink.xact_rep)
io.tilelink.xact_finish <> Queue(arbiter.io.mem.xact_finish)
dcache.io.mem.probe_req <> Queue(io.tilelink.probe_req)
io.tilelink.probe_rep <> Queue(dcache.io.mem.probe_rep, 1)
io.tilelink.probe_rep_data <> Queue(dcache.io.mem.probe_rep_data)
if (HAVE_VEC)
{
val vicache = new rocketICache(128, 1) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem
cpu.io.vimem <> vicache.io.cpu
}
cpu.io.host <> io.host
icache_pf.io.invalidate := cpu.io.imem.invalidate
icache.io.mem <> icache_pf.io.icache
cpu.io.imem <> icache.io.cpu
cpu.io.dmem <> dcache.io.cpu
}

41
rocket/src/main/scala/top.scala
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@ -15,41 +15,18 @@ class Top() extends Component {
val htif_width = 16
val io = new ioTop(htif_width);
val tile = new Tile
val htif = new rocketHTIF(htif_width, 1)
val cpu = new rocketProc(resetSignal = htif.io.cpu(0).reset);
val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB)
val icache_pf = new rocketIPrefetcher();
val dcache = new HellaCacheUniproc();
val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0));
arbiter.io.requestor(0) <> dcache.io.mem
arbiter.io.requestor(1) <> icache_pf.io.mem
val hub = new CoherenceHubBroadcast(2)
// connect tile to hub
hub.io.tiles(0).xact_init <> Queue(arbiter.io.mem.xact_init)
hub.io.tiles(0).xact_init_data <> Queue(dcache.io.mem.xact_init_data)
arbiter.io.mem.xact_abort <> Queue(hub.io.tiles(0).xact_abort)
arbiter.io.mem.xact_rep <> Pipe(hub.io.tiles(0).xact_rep)
hub.io.tiles(0).xact_finish <> Queue(arbiter.io.mem.xact_finish)
dcache.io.mem.probe_req <> Queue(hub.io.tiles(0).probe_req)
hub.io.tiles(0).probe_rep <> Queue(dcache.io.mem.probe_rep, 1)
hub.io.tiles(0).probe_rep_data <> Queue(dcache.io.mem.probe_rep_data)
// connect HTIF to hub
hub.io.tiles(0) <> tile.io.tilelink
hub.io.tiles(1) <> htif.io.mem
// connect hub to memory
io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
io.mem.req_data <> Queue(hub.io.mem.req_data)
hub.io.mem.resp <> Pipe(io.mem.resp)
if (HAVE_VEC)
{
val vicache = new rocketICache(128, 1); // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem
cpu.io.vimem <> vicache.io.cpu;
}
// pad out the HTIF using a divided clock
val slow_io = (new slowIO(64, 16)) { Bits(width = htif_width) }
htif.io.host.out <> slow_io.io.out_fast
@ -58,14 +35,8 @@ class Top() extends Component {
io.host.in <> slow_io.io.in_slow
io.host_clk := slow_io.io.clk_slow
cpu.io.host <> htif.io.cpu(0);
cpu.io.debug <> io.debug;
icache_pf.io.invalidate := cpu.io.imem.invalidate
icache.io.mem <> icache_pf.io.icache;
cpu.io.imem <> icache.io.cpu;
cpu.io.dmem <> dcache.io.cpu;
tile.io.host <> htif.io.cpu(0)
io.debug <> tile.io.host.debug
}
object top_main {