use divided clk for htif. UDPATE YOUR FESVR
by default, we now load programs via a backdoor, because otherwise it takes too long to simulate.
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49
rocket/src/main/scala/slowio.scala
Normal file
49
rocket/src/main/scala/slowio.scala
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@ -0,0 +1,49 @@
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package rocket
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import Chisel._
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import Constants._
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class slowIO[T <: Data](divisor: Int, hold_cycles: Int)(data: => T) extends Component
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{
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val io = new Bundle {
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val out_fast = new ioDecoupled()(data).flip
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val out_slow = new ioDecoupled()(data)
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val in_fast = new ioDecoupled()(data)
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val in_slow = new ioDecoupled()(data).flip
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val clk_slow = Bool(OUTPUT)
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}
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require((divisor & (divisor-1)) == 0)
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require(hold_cycles < divisor/2 && hold_cycles >= 2)
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val cnt = Reg() { UFix(width = log2up(divisor)) }
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cnt := cnt + UFix(1)
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val out_en = cnt === UFix(divisor/2+hold_cycles-1) // rising edge + hold time
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val in_en = cnt === UFix(divisor/2-1) // rising edge
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val in_slow_rdy = Reg(resetVal = Bool(false))
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val out_slow_val = Reg(resetVal = Bool(false))
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val out_slow_bits = Reg() { data }
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val fromhost_q = new queue(1)(data)
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fromhost_q.io.enq.valid := in_en && io.in_slow.valid && in_slow_rdy
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fromhost_q.io.enq.bits := io.in_slow.bits
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fromhost_q.io.deq <> io.in_fast
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val tohost_q = new queue(1)(data)
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tohost_q.io.enq <> io.out_fast
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tohost_q.io.deq.ready := in_en && io.out_slow.ready && out_slow_val
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when (out_en) {
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in_slow_rdy := fromhost_q.io.enq.ready
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out_slow_val := tohost_q.io.deq.valid
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out_slow_bits := tohost_q.io.deq.bits
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}
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io.in_slow.ready := in_slow_rdy
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io.out_slow.valid := out_slow_val
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io.out_slow.bits := out_slow_bits
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io.clk_slow := cnt(log2up(divisor)-1).toBool
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}
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@ -7,6 +7,7 @@ import Constants._;
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class ioTop(htif_width: Int) extends Bundle {
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val debug = new ioDebug();
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val host = new ioHost(htif_width);
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val host_clk = Bool(OUTPUT)
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val mem = new ioMem
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}
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@ -49,7 +50,14 @@ class Top() extends Component {
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cpu.io.vimem <> vicache.io.cpu;
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}
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htif.io.host <> io.host
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// pad out the HTIF using a divided clock
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val slow_io = (new slowIO(64, 16)) { Bits(width = htif_width) }
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htif.io.host.out <> slow_io.io.out_fast
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io.host.out <> slow_io.io.out_slow
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htif.io.host.in <> slow_io.io.in_fast
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io.host.in <> slow_io.io.in_slow
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io.host_clk := slow_io.io.clk_slow
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cpu.io.host <> htif.io.cpu(0);
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cpu.io.debug <> io.debug;
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