riscv/rocket-chip
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add IPIs and an IPI test

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IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
This commit is contained in:
Andrew Waterman 2012-05-08 22:58:00 -07:00
parent 87cbae2c8a
commit e0e1cd5d32
3 changed files with 23 additions and 9 deletions
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8
rocket/src/main/scala/dpath_util.scala
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@ -115,7 +115,7 @@ class rocketDpathPCR extends Component
val reg_status_et = Reg(resetVal = Bool(false));
val r_irq_timer = Reg(resetVal = Bool(false));
val r_irq_ipi = Reg(resetVal = Bool(false));
val r_irq_ipi = Reg(resetVal = Bool(true))
val rdata = Wire() { Bits() };
@ -174,6 +174,8 @@ class rocketDpathPCR extends Component
io.irq_timer := r_irq_timer;
io.irq_ipi := r_irq_ipi;
io.host.ipi.valid := Bool(false)
io.host.ipi.bits := wdata
when (wen) {
when (waddr === PCR_STATUS) {
@ -194,8 +196,8 @@ class rocketDpathPCR extends Component
when (waddr === PCR_COMPARE) { reg_compare := wdata(31,0).toUFix; r_irq_timer := Bool(false); }
when (waddr === PCR_FROMHOST) { reg_fromhost := wdata; reg_tohost := Bits(0) }
when (waddr === PCR_TOHOST) { reg_tohost := wdata; reg_fromhost := Bits(0) }
when (waddr === PCR_SEND_IPI) { r_irq_ipi := Bool(true); }
when (waddr === PCR_CLR_IPI) { r_irq_ipi := Bool(false); }
when (waddr === PCR_SEND_IPI) { io.host.ipi.valid := Bool(true) }
when (waddr === PCR_CLR_IPI) { r_irq_ipi := wdata(0) }
when (waddr === PCR_K0) { reg_k0 := wdata; }
when (waddr === PCR_K1) { reg_k1 := wdata; }
when (waddr === PCR_PTBR) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }

22
rocket/src/main/scala/htif.scala
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@ -28,6 +28,7 @@ class ioHTIF extends Bundle
val debug = new ioDebug
val pcr_req = (new ioDecoupled) { new PCRReq }.flip
val pcr_rep = (new ioPipe) { Bits(width = 64) }
val ipi = (new ioDecoupled) { Bits(width = log2up(NTILES)) }
}
class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends Component
@ -194,18 +195,29 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
val pcr_mux = (new Mux1H(ncores)) { Bits(width = 64) }
for (i <- 0 until ncores) {
val my_reset = Reg(resetVal = Bool(true))
val my_ipi = Reg(resetVal = Bool(false))
val rdata = Reg() { Bits() }
val cpu = io.cpu(i)
val me = pcr_coreid === UFix(i)
cpu.pcr_req.valid := state === state_pcr && me
cpu.pcr_req.bits.rw := cmd === cmd_writecr
cpu.pcr_req.bits.addr := pcr_addr
cpu.pcr_req.bits.data := pcr_wdata
cpu.pcr_req.valid := my_ipi || state === state_pcr && me
cpu.pcr_req.bits.rw := my_ipi || cmd === cmd_writecr
cpu.pcr_req.bits.addr := Mux(my_ipi, PCR_CLR_IPI, pcr_addr)
cpu.pcr_req.bits.data := my_ipi | pcr_wdata
cpu.reset := my_reset
for (j <- 0 until ncores) {
when (io.cpu(j).ipi.valid && io.cpu(j).ipi.bits === UFix(i)) {
my_ipi := Bool(true)
my_reset := Bool(false)
}
}
when (my_ipi) {
my_ipi := !cpu.pcr_req.ready
}
when (state === state_pcr && me && cmd === cmd_writecr) {
pcr_done := cpu.pcr_req.ready
pcr_done := cpu.pcr_req.ready && !my_ipi
when (pcr_addr === PCR_RESET) {
my_reset := pcr_wdata(0)
}

2
rocket/src/main/scala/instructions.scala
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@ -255,5 +255,5 @@ object Instructions
val VXCPTEVAC = Bits("b00000_?????_00000_0001000110_1111011",32)
val VXCPTHOLD = Bits("b00000_00000_00000_0001001110_1111011",32)
val NOP = ADDI & Bits("b00000000000000000000001111111111", 32);
val NOP = Bits("b00000_00000_000000000000_000_0010011",32);
}