riscv/rocket-chip
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fix pseudo-LRU verilog generation bug

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This commit is contained in:
Andrew Waterman 2012-05-02 19:27:27 -07:00
parent 622a801bb1
commit 2d4e5d3813
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/itlb.scala
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@ -56,7 +56,7 @@ class PseudoLRU(n: Int)
var idx = UFix(1,1)
for (i <- log2up(n)-1 to 0 by -1) {
val bit = way(i)
val mask = (UFix(1) << idx)(n-1,0)
val mask = (UFix(1,n) << idx)(n-1,0)
next_state = next_state & ~mask | Mux(bit, UFix(0), mask)
//next_state.bitSet(idx, !bit)
idx = Cat(idx, bit)