clean up cache interfaces; avoid reserved keywords
This commit is contained in:
Andrew Waterman
parent
820884c7e6
commit
cfca2d1411
@ -38,7 +38,7 @@ class rocketDpathALU extends Component
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val shin = Mux(shright, shin_r, Reverse(shin_r))
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val shout_r = (Cat(sra & shin_r(63), shin).toFix >> shamt)(63,0)
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val logic =
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val bitwise_logic =
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Mux(io.fn === FN_AND, io.in1 & io.in2,
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Mux(io.fn === FN_OR, io.in1 | io.in2,
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Mux(io.fn === FN_XOR, io.in1 ^ io.in2,
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@ -49,7 +49,7 @@ class rocketDpathALU extends Component
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Mux(io.fn === FN_SLT || io.fn === FN_SLTU, less,
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Mux(io.fn === FN_SR || io.fn === FN_SRA, shout_r,
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Mux(io.fn === FN_SL, Reverse(shout_r),
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logic))))
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bitwise_logic))))
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val out_hi = Mux(io.dw === DW_64, out64(63,32), Fill(32, out64(31)))
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io.out := Cat(out_hi, out64(31,0)).toUFix
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@ -29,9 +29,9 @@ class StoreMaskGen extends Component {
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val word = (io.typ === MT_W) || (io.typ === MT_WU)
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val half = (io.typ === MT_H) || (io.typ === MT_HU)
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val byte = (io.typ === MT_B) || (io.typ === MT_BU)
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val byte_ = (io.typ === MT_B) || (io.typ === MT_BU)
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io.wmask := Mux(byte, Bits( 1,1) << io.addr(2,0).toUFix,
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io.wmask := Mux(byte_, Bits( 1,1) << io.addr(2,0).toUFix,
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Mux(half, Bits( 3,2) << Cat(io.addr(2,1), Bits(0,1)).toUFix,
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Mux(word, Bits( 15,4) << Cat(io.addr(2), Bits(0,2)).toUFix,
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Bits(255,8))));
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@ -46,9 +46,9 @@ class StoreDataGen extends Component {
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val word = (io.typ === MT_W) || (io.typ === MT_WU)
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val half = (io.typ === MT_H) || (io.typ === MT_HU)
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val byte = (io.typ === MT_B) || (io.typ === MT_BU)
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val byte_ = (io.typ === MT_B) || (io.typ === MT_BU)
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io.dout := Mux(byte, Fill(8, io.din( 7,0)),
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io.dout := Mux(byte_, Fill(8, io.din( 7,0)),
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Mux(half, Fill(4, io.din(15,0)),
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Mux(word, Fill(2, io.din(31,0)),
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io.din)))
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@ -69,7 +69,7 @@ class LoadDataGen extends Component {
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(io.typ === MT_W) || (io.typ === MT_D)
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val word = (io.typ === MT_W) || (io.typ === MT_WU)
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val half = (io.typ === MT_H) || (io.typ === MT_HU)
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val byte = (io.typ === MT_B) || (io.typ === MT_BU)
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val byte_ = (io.typ === MT_B) || (io.typ === MT_BU)
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val shifted = io.din >> Cat(io.addr(io.addr.width-1,2), Bits(0, 5)).toUFix
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val extended =
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@ -78,7 +78,7 @@ class LoadDataGen extends Component {
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val r_extended = Reg(extended)
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val r_sext = Reg(sext)
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val r_half = Reg(half)
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val r_byte = Reg(byte)
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val r_byte = Reg(byte_)
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val r_addr = Reg(io.addr)
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val shifted_subword = r_extended >> Cat(r_addr(1,0), Bits(0, 3)).toUFix
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@ -131,6 +131,7 @@ class DataReq extends Bundle {
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}
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class DataArrayReq extends Bundle {
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val way_en = Bits(width = NWAYS)
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val idx = Bits(width = IDX_BITS)
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val offset = Bits(width = log2up(REFILL_CYCLES))
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val rw = Bool()
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@ -138,11 +139,6 @@ class DataArrayReq extends Bundle {
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val data = Bits(width = MEM_DATA_BITS)
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}
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class DataArrayArrayReq extends Bundle {
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val inner_req = new DataArrayReq()
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val way_en = Bits(width = NWAYS)
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}
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class WritebackReq extends Bundle {
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val tag = Bits(width = TAG_BITS)
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val idx = Bits(width = IDX_BITS)
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@ -156,16 +152,12 @@ class MetaData extends Bundle {
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}
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class MetaArrayReq extends Bundle {
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val way_en = Bits(width = NWAYS)
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val idx = Bits(width = IDX_BITS)
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val rw = Bool()
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val data = new MetaData()
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}
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class MetaArrayArrayReq extends Bundle {
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val inner_req = new MetaArrayReq()
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val way_en = Bits(width = NWAYS)
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}
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class MSHR(id: Int) extends Component with FourStateCoherence {
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val io = new Bundle {
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val req_pri_val = Bool(INPUT)
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@ -182,7 +174,7 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
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val way_oh = Bits(NWAYS, OUTPUT)
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val mem_req = (new ioDecoupled) { new TransactionInit }
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val meta_req = (new ioDecoupled) { new MetaArrayArrayReq() }
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val meta_req = (new ioDecoupled) { new MetaArrayReq() }
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val replay = (new ioDecoupled) { new Replay() }
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val mem_abort = (new ioPipe) { new TransactionAbort }.flip
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val mem_rep = (new ioPipe) { new TransactionReply }.flip
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@ -270,10 +262,10 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
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io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
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io.meta_req.valid := (state === s_drain_rpq) && !rpq.io.deq.valid && !finish_q.io.deq.valid
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io.meta_req.bits.inner_req.rw := Bool(true)
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io.meta_req.bits.inner_req.idx := req.idx
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io.meta_req.bits.inner_req.data.state := line_state
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io.meta_req.bits.inner_req.data.tag := req.tag
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io.meta_req.bits.rw := Bool(true)
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io.meta_req.bits.idx := req.idx
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io.meta_req.bits.data.state := line_state
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io.meta_req.bits.data.tag := req.tag
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io.meta_req.bits.way_en := req.way_oh
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io.wb_req.valid := (state === s_wb_req)
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@ -309,7 +301,7 @@ class MSHRFile extends Component {
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val fence_rdy = Bool(OUTPUT)
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val mem_req = (new ioDecoupled) { new TransactionInit }
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val meta_req = (new ioDecoupled) { new MetaArrayArrayReq() }
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val meta_req = (new ioDecoupled) { new MetaArrayReq() }
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val data_req = (new ioDecoupled) { new DataReq() }
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val mem_abort = (new ioPipe) { new TransactionAbort }.flip
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val mem_rep = (new ioPipe) { new TransactionReply }.flip
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@ -332,8 +324,8 @@ class MSHRFile extends Component {
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val tag_mux = (new Mux1H(NMSHR)){ Bits(width = TAG_BITS) }
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val wb_probe_mux = (new Mux1H(NMSHR)) { new WritebackReq }
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val mem_resp_mux = (new Mux1H(NMSHR)){ new DataArrayArrayReq }
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val meta_req_arb = (new Arbiter(NMSHR)) { new MetaArrayArrayReq() }
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val mem_resp_mux = (new Mux1H(NMSHR)){ new DataArrayReq }
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val meta_req_arb = (new Arbiter(NMSHR)) { new MetaArrayReq() }
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val mem_req_arb = (new Arbiter(NMSHR)) { new TransactionInit }
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val mem_finish_arb = (new Arbiter(NMSHR)) { new TransactionFinish }
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val wb_req_arb = (new Arbiter(NMSHR)) { new WritebackReq }
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@ -376,8 +368,8 @@ class MSHRFile extends Component {
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mshr.io.mem_abort <> io.mem_abort
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mshr.io.mem_rep <> io.mem_rep
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mem_resp_mux.io.sel(i) := UFix(i) === io.mem_rep.bits.tile_xact_id
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mem_resp_mux.io.in(i).inner_req.idx := mshr.io.idx
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mem_resp_mux.io.in(i).inner_req.offset := mshr.io.refill_count
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mem_resp_mux.io.in(i).idx := mshr.io.idx
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mem_resp_mux.io.in(i).offset := mshr.io.refill_count
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mem_resp_mux.io.in(i).way_en := mshr.io.way_oh
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pri_rdy = pri_rdy || mshr.io.req_pri_rdy
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@ -397,8 +389,8 @@ class MSHRFile extends Component {
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io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
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io.secondary_miss := idx_match
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io.mem_resp_idx := mem_resp_mux.io.out.inner_req.idx
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io.mem_resp_offset := mem_resp_mux.io.out.inner_req.offset
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io.mem_resp_idx := mem_resp_mux.io.out.idx
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io.mem_resp_offset := mem_resp_mux.io.out.offset
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io.mem_resp_way_oh := mem_resp_mux.io.out.way_en
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io.fence_rdy := !fence
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io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match)
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@ -421,7 +413,7 @@ class WritebackUnit extends Component {
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val io = new Bundle {
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val req = (new ioDecoupled) { new WritebackReq() }.flip
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val probe = (new ioDecoupled) { new WritebackReq() }.flip
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val data_req = (new ioDecoupled) { new DataArrayArrayReq() }
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val data_req = (new ioDecoupled) { new DataArrayReq() }
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val data_resp = Bits(MEM_DATA_BITS, INPUT)
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val mem_req = (new ioDecoupled) { new TransactionInit }
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val mem_req_data = (new ioDecoupled) { new TransactionInitData }
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@ -470,11 +462,11 @@ class WritebackUnit extends Component {
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io.probe.ready := !valid
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io.data_req.valid := valid && (cnt < UFix(REFILL_CYCLES))
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io.data_req.bits.way_en := req.way_oh
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io.data_req.bits.inner_req.idx := req.idx
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io.data_req.bits.inner_req.offset := cnt
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io.data_req.bits.inner_req.rw := Bool(false)
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io.data_req.bits.inner_req.wmask := Bits(0)
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io.data_req.bits.inner_req.data := Bits(0)
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io.data_req.bits.idx := req.idx
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io.data_req.bits.offset := cnt
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io.data_req.bits.rw := Bool(false)
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io.data_req.bits.wmask := Bits(0)
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io.data_req.bits.data := Bits(0)
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io.mem_req.valid := valid && !cmd_sent
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io.mem_req.bits.t_type := X_INIT_WRITE_UNCACHED
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@ -490,7 +482,7 @@ class ProbeUnit extends Component with FourStateCoherence {
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val io = new Bundle {
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val req = (new ioDecoupled) { new ProbeRequest }.flip
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val rep = (new ioDecoupled) { new ProbeReply }
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val meta_req = (new ioDecoupled) { new MetaArrayArrayReq }
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val meta_req = (new ioDecoupled) { new MetaArrayReq }
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val mshr_req = (new ioDecoupled) { Bool() }
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val wb_req = (new ioDecoupled) { new WritebackReq }
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val tag_match_way_oh = Bits(NWAYS, INPUT)
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@ -533,10 +525,10 @@ class ProbeUnit extends Component with FourStateCoherence {
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io.meta_req.valid := state === s_meta_req || state === s_meta_resp || state === s_probe_rep && hit
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io.meta_req.bits.way_en := Mux(state === s_probe_rep, way_oh, ~UFix(0, NWAYS))
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io.meta_req.bits.inner_req.rw := state === s_probe_rep
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io.meta_req.bits.inner_req.idx := req.address
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io.meta_req.bits.inner_req.data.state := newStateOnProbeReq(req, line_state)
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io.meta_req.bits.inner_req.data.tag := req.address >> UFix(IDX_BITS)
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io.meta_req.bits.rw := state === s_probe_rep
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io.meta_req.bits.idx := req.address
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io.meta_req.bits.data.state := newStateOnProbeReq(req, line_state)
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io.meta_req.bits.data.tag := req.address >> UFix(IDX_BITS)
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io.mshr_req.valid := state === s_meta_resp
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io.address := req.address
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@ -549,7 +541,7 @@ class ProbeUnit extends Component with FourStateCoherence {
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class FlushUnit(lines: Int) extends Component with FourStateCoherence{
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val io = new Bundle {
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val req = (new ioDecoupled) { Bool() }.flip
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val meta_req = (new ioDecoupled) { new MetaArrayArrayReq() }
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val meta_req = (new ioDecoupled) { new MetaArrayReq() }
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val mshr_req = (new ioDecoupled) { Bool() }
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}
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@ -589,10 +581,10 @@ class FlushUnit(lines: Int) extends Component with FourStateCoherence{
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io.mshr_req.valid := state === s_meta_wait
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io.meta_req.valid := (state === s_meta_read) || (state === s_reset)
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io.meta_req.bits.way_en := UFixToOH(way_cnt, NWAYS)
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io.meta_req.bits.inner_req.idx := idx_cnt
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io.meta_req.bits.inner_req.rw := (state === s_reset)
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io.meta_req.bits.inner_req.data.state := newStateOnFlush()
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io.meta_req.bits.inner_req.data.tag := UFix(0)
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io.meta_req.bits.idx := idx_cnt
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io.meta_req.bits.rw := (state === s_reset)
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io.meta_req.bits.data.state := newStateOnFlush()
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io.meta_req.bits.data.tag := UFix(0)
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}
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class MetaDataArray(lines: Int) extends Component {
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@ -621,9 +613,9 @@ class MetaDataArray(lines: Int) extends Component {
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class MetaDataArrayArray(lines: Int) extends Component {
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val io = new Bundle {
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val req = (new ioDecoupled) { new MetaArrayArrayReq() }.flip
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val req = (new ioDecoupled) { new MetaArrayReq() }.flip
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val resp = Vec(NWAYS){ (new MetaData).asOutput }
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val state_req = (new ioDecoupled) { new MetaArrayArrayReq() }.flip
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val state_req = (new ioDecoupled) { new MetaArrayReq() }.flip
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val way_en = Bits(width = NWAYS, dir = OUTPUT)
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}
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@ -632,22 +624,18 @@ class MetaDataArrayArray(lines: Int) extends Component {
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way_en_ := io.req.bits.way_en
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}
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var tag_ready = Bool(true)
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var state_ready = Bool(true)
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for(w <- 0 until NWAYS) {
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val way = new MetaDataArray(lines)
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way.io.req.bits <> io.req.bits.inner_req
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tag_ready = tag_ready && way.io.req.ready
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way.io.req.bits <> io.req.bits
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way.io.req.valid := io.req.valid && io.req.bits.way_en(w).toBool
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way.io.state_req.bits <> io.state_req.bits.inner_req
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state_ready = state_ready && way.io.state_req.ready
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way.io.state_req.bits <> io.state_req.bits
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way.io.state_req.valid := io.state_req.valid && io.state_req.bits.way_en(w).toBool
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way.io.resp <> io.resp(w)
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}
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io.way_en := way_en_
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io.req.ready := tag_ready
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io.state_req.ready := state_ready
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io.req.ready := Bool(true)
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io.state_req.ready := Bool(true)
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}
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class DataArray(lines: Int) extends Component {
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@ -669,7 +657,7 @@ class DataArray(lines: Int) extends Component {
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class DataArrayArray(lines: Int) extends Component {
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val io = new Bundle {
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val req = (new ioDecoupled) { new DataArrayArrayReq() }.flip
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val req = (new ioDecoupled) { new DataArrayReq() }.flip
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val resp = Vec(NWAYS){ Bits(width = MEM_DATA_BITS, dir = OUTPUT) }
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val way_en = Bits(width = NWAYS, dir = OUTPUT)
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}
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@ -679,20 +667,15 @@ class DataArrayArray(lines: Int) extends Component {
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way_en_ := io.req.bits.way_en
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}
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//val data_ready_arr = Vec(NWAYS){ Bool() }
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var data_ready = Bool(true)
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for(w <- 0 until NWAYS) {
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val way = new DataArray(lines)
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way.io.req.bits <> io.req.bits.inner_req
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//data_ready_arr(w) := way.io.req.ready
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data_ready = data_ready && way.io.req.ready
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way.io.req.bits <> io.req.bits
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way.io.req.valid := io.req.valid && io.req.bits.way_en(w).toBool
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way.io.resp <> io.resp(w)
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}
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io.way_en := way_en_
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//io.req.ready := Cat(data_ready_arr).andR.toBool
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io.req.ready := data_ready
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io.req.ready := Bool(true)
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}
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class AMOALU extends Component {
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@ -837,10 +820,10 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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r_way_oh := mshr.io.data_req.bits.way_oh
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}
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when (prober.io.meta_req.valid) {
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r_cpu_req_idx := Cat(prober.io.meta_req.bits.inner_req.data.tag, prober.io.meta_req.bits.inner_req.idx, mshr.io.data_req.bits.offset)(PGIDX_BITS-1,0)
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r_cpu_req_idx := Cat(prober.io.meta_req.bits.data.tag, prober.io.meta_req.bits.idx, mshr.io.data_req.bits.offset)(PGIDX_BITS-1,0)
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}
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when (flusher.io.meta_req.valid) {
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r_cpu_req_idx := Cat(flusher.io.meta_req.bits.inner_req.idx, mshr.io.data_req.bits.offset)
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r_cpu_req_idx := Cat(flusher.io.meta_req.bits.idx, mshr.io.data_req.bits.offset)
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r_cpu_req_cmd := M_FLA
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r_way_oh := flusher.io.meta_req.bits.way_en
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}
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@ -856,19 +839,19 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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// tags
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val meta = new MetaDataArrayArray(lines)
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val meta_arb = (new Arbiter(4)) { new MetaArrayArrayReq() }
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val meta_arb = (new Arbiter(4)) { new MetaArrayReq() }
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flusher.io.meta_req <> meta_arb.io.in(0)
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meta_arb.io.out <> meta.io.req
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// data
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val data = new DataArrayArray(lines)
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val data_arb = (new Arbiter(5)) { new DataArrayArrayReq() }
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val data_arb = (new Arbiter(5)) { new DataArrayReq() }
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data_arb.io.out <> data.io.req
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// cpu tag check
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meta_arb.io.in(3).valid := io.cpu.req_val
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meta_arb.io.in(3).bits.inner_req.idx := io.cpu.req_idx(indexmsb,indexlsb)
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meta_arb.io.in(3).bits.inner_req.rw := Bool(false)
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||||
meta_arb.io.in(3).bits.idx := io.cpu.req_idx(indexmsb,indexlsb)
|
||||
meta_arb.io.in(3).bits.rw := Bool(false)
|
||||
meta_arb.io.in(3).bits.way_en := ~UFix(0, NWAYS)
|
||||
val early_tag_nack = !meta_arb.io.in(3).ready
|
||||
val cpu_req_ppn = Mux(prober.io.mshr_req.valid, prober.io.address >> UFix(PGIDX_BITS-OFFSET_BITS), io.cpu.req_ppn)
|
||||
@ -905,18 +888,18 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
|
||||
val meta_wb_mux = Mux1H(replaced_way_oh, meta.io.resp)
|
||||
|
||||
// refill response
|
||||
data_arb.io.in(0).bits.inner_req.offset := mshr.io.mem_resp_offset
|
||||
data_arb.io.in(0).bits.inner_req.idx := mshr.io.mem_resp_idx
|
||||
data_arb.io.in(0).bits.inner_req.rw := Bool(true)
|
||||
data_arb.io.in(0).bits.inner_req.wmask := ~UFix(0, MEM_DATA_BITS/8)
|
||||
data_arb.io.in(0).bits.inner_req.data := io.mem.xact_rep.bits.data
|
||||
data_arb.io.in(0).bits.offset := mshr.io.mem_resp_offset
|
||||
data_arb.io.in(0).bits.idx := mshr.io.mem_resp_idx
|
||||
data_arb.io.in(0).bits.rw := Bool(true)
|
||||
data_arb.io.in(0).bits.wmask := ~UFix(0, MEM_DATA_BITS/8)
|
||||
data_arb.io.in(0).bits.data := io.mem.xact_rep.bits.data
|
||||
data_arb.io.in(0).bits.way_en := mshr.io.mem_resp_way_oh
|
||||
data_arb.io.in(0).valid := io.mem.xact_rep.valid && (io.mem.xact_rep.bits.t_type === X_REP_READ_SHARED || io.mem.xact_rep.bits.t_type === X_REP_READ_EXCLUSIVE)
|
||||
|
||||
// load hits
|
||||
data_arb.io.in(4).bits.inner_req.offset := io.cpu.req_idx(offsetmsb,ramindexlsb)
|
||||
data_arb.io.in(4).bits.inner_req.idx := io.cpu.req_idx(indexmsb,indexlsb)
|
||||
data_arb.io.in(4).bits.inner_req.rw := Bool(false)
|
||||
data_arb.io.in(4).bits.offset := io.cpu.req_idx(offsetmsb,ramindexlsb)
|
||||
data_arb.io.in(4).bits.idx := io.cpu.req_idx(indexmsb,indexlsb)
|
||||
data_arb.io.in(4).bits.rw := Bool(false)
|
||||
data_arb.io.in(4).valid := io.cpu.req_val && req_read
|
||||
data_arb.io.in(4).bits.way_en := ~UFix(0, NWAYS) // intiate load on all ways, mux after tag check
|
||||
val early_load_nack = req_read && !data_arb.io.in(4).ready
|
||||
@ -929,9 +912,9 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
|
||||
val p_store_offset_match = (r_cpu_req_idx(indexlsb-1,offsetlsb) === p_store_idx(indexlsb-1,offsetlsb))
|
||||
val p_store_match = r_cpu_req_val_ && r_req_read && p_store_idx_match && p_store_offset_match
|
||||
val drain_store_val = (p_store_valid && (!io.cpu.req_val || !req_read || wb.io.data_req.valid || mshr.io.data_req.valid)) || p_store_match
|
||||
data_arb.io.in(2).bits.inner_req.offset := p_store_idx(offsetmsb,ramindexlsb)
|
||||
data_arb.io.in(2).bits.inner_req.idx := p_store_idx(indexmsb,indexlsb)
|
||||
data_arb.io.in(2).bits.inner_req.rw := Bool(true)
|
||||
data_arb.io.in(2).bits.offset := p_store_idx(offsetmsb,ramindexlsb)
|
||||
data_arb.io.in(2).bits.idx := p_store_idx(indexmsb,indexlsb)
|
||||
data_arb.io.in(2).bits.rw := Bool(true)
|
||||
data_arb.io.in(2).valid := drain_store_val
|
||||
data_arb.io.in(2).bits.way_en := p_store_way_oh
|
||||
val drain_store = drain_store_val && data_arb.io.in(2).ready
|
||||
@ -943,9 +926,9 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
|
||||
// tag update after a store to an exclusive clean line.
|
||||
val new_hit_state = newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state)
|
||||
val set_hit_state = r_cpu_req_val && tag_hit && meta_resp_mux.state != new_hit_state
|
||||
meta.io.state_req.bits.inner_req.rw := Bool(true)
|
||||
meta.io.state_req.bits.inner_req.idx := Reg(r_cpu_req_idx(indexmsb,indexlsb))
|
||||
meta.io.state_req.bits.inner_req.data.state := Reg(new_hit_state)
|
||||
meta.io.state_req.bits.rw := Bool(true)
|
||||
meta.io.state_req.bits.idx := Reg(r_cpu_req_idx(indexmsb,indexlsb))
|
||||
meta.io.state_req.bits.data.state := Reg(new_hit_state)
|
||||
meta.io.state_req.bits.way_en := Reg(tag_match_way_oh)
|
||||
meta.io.state_req.valid := Reg(set_hit_state, resetVal = Bool(false))
|
||||
|
||||
@ -988,9 +971,9 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
|
||||
val replay_val = mshr.io.data_req.valid
|
||||
val replay_fire = replay_val && !stall_replay
|
||||
val replay_rdy = data_arb.io.in(1).ready && !stall_replay
|
||||
data_arb.io.in(1).bits.inner_req.offset := replay.offset(offsetmsb,ramindexlsb)
|
||||
data_arb.io.in(1).bits.inner_req.idx := replay.idx
|
||||
data_arb.io.in(1).bits.inner_req.rw := replay.cmd === M_XWR
|
||||
data_arb.io.in(1).bits.offset := replay.offset(offsetmsb,ramindexlsb)
|
||||
data_arb.io.in(1).bits.idx := replay.idx
|
||||
data_arb.io.in(1).bits.rw := replay.cmd === M_XWR
|
||||
data_arb.io.in(1).valid := replay_fire
|
||||
data_arb.io.in(1).bits.way_en := mshr.io.data_req.bits.way_oh
|
||||
mshr.io.data_req.ready := replay_rdy
|
||||
@ -1005,10 +988,10 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
|
||||
val store_wmask_wide = maskgen.io.wmask << Cat(store_offset(ramindexlsb-1,offsetlsb), Bits(0, log2up(CPU_DATA_BITS/8))).toUFix
|
||||
val store_data = Mux(!replay_fire, p_store_data, replay.data)
|
||||
val store_data_wide = Fill(MEM_DATA_BITS/CPU_DATA_BITS, store_data)
|
||||
data_arb.io.in(1).bits.inner_req.data := store_data_wide
|
||||
data_arb.io.in(1).bits.inner_req.wmask := store_wmask_wide
|
||||
data_arb.io.in(2).bits.inner_req.data := store_data_wide
|
||||
data_arb.io.in(2).bits.inner_req.wmask := store_wmask_wide
|
||||
data_arb.io.in(1).bits.data := store_data_wide
|
||||
data_arb.io.in(1).bits.wmask := store_wmask_wide
|
||||
data_arb.io.in(2).bits.data := store_data_wide
|
||||
data_arb.io.in(2).bits.wmask := store_wmask_wide
|
||||
|
||||
// load data subword mux/sign extension.
|
||||
// subword loads are delayed by one cycle.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user