remove faulting TLB entry after page fault
this vastly reduces the frequency with which the TLB must be flushed
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parent
6d8fc74378
commit
a0378c5d2f
@ -79,6 +79,7 @@ class rocketDTLB(entries: Int) extends Component
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val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
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tag_cam.io.clear := io.invalidate;
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tag_cam.io.clear_hit := io.cpu_resp.xcpt_ld || io.cpu_resp.xcpt_st || io.cpu_resp.xcpt_pf
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tag_cam.io.tag := lookup_tag;
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tag_cam.io.write := io.ptw.resp_val || io.ptw.resp_err;
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tag_cam.io.write_tag := r_refill_tag;
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@ -7,6 +7,7 @@ import scala.math._;
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class ioCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
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val clear = Bool(INPUT);
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val clear_hit = Bool(INPUT)
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val tag = Bits(tag_bits, INPUT);
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val hit = Bool(OUTPUT);
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val hit_addr = UFix(addr_bits, OUTPUT);
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@ -21,17 +22,20 @@ class rocketCAM(entries: Int, tag_bits: Int) extends Component {
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val addr_bits = ceil(log(entries)/log(2)).toInt;
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val io = new ioCAM(entries, addr_bits, tag_bits);
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val cam_tags = Mem(entries, io.write, io.write_addr, io.write_tag);
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val mux = (new Mux1H(entries)) { Bits(width = addr_bits) }
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val vb_array = Reg(resetVal = Bits(0, entries));
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when (io.clear) {
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vb_array := Bits(0, entries);
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}
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.elsewhen (io.clear_hit) {
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vb_array := vb_array & ~mux.io.sel.toBits
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}
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.elsewhen (io.write) {
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vb_array := vb_array.bitSet(io.write_addr, Bool(true));
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}
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var l_hit = Bool(false)
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val mux = (new Mux1H(entries)) { Bits(width = addr_bits) }
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for (i <- 0 to entries-1) {
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val my_hit = vb_array(UFix(i)).toBool && (cam_tags(UFix(i)) === io.tag)
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l_hit = l_hit || my_hit
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@ -114,6 +118,7 @@ class rocketITLB(entries: Int) extends Component
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val lookup_tag = Cat(r_cpu_req_asid, r_cpu_req_vpn);
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tag_cam.io.clear := io.cpu.invalidate;
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tag_cam.io.clear_hit := io.cpu.exception
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tag_cam.io.tag := lookup_tag;
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tag_cam.io.write := io.ptw.resp_val || io.ptw.resp_err;
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tag_cam.io.write_tag := r_refill_tag;
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