add probe unit
This commit is contained in:
Andrew Waterman
parent
fdffb124e3
commit
b0f798962c
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@ -135,6 +135,12 @@ trait ThreeStateIncoherence extends CoherencePolicy {
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Mux(outstanding.t_type === X_INIT_READ_EXCLUSIVE, tileDirty, tileClean)
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}
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def newStateOnProbeReq(incoming: ProbeRequest, state: UFix): Bits = state
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def newProbeReply (incoming: ProbeRequest, has_data: Bool): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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reply.p_type := P_REP_INVALIDATE_ACK
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reply.global_xact_id := UFix(0)
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reply
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}
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def probeReplyHasData (reply: ProbeReply): Bool = Bool(false)
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def transactionInitHasData (init: TransactionInit): Bool = (init.t_type === X_INIT_WRITE_UNCACHED)
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}
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@ -199,6 +205,22 @@ trait FourStateCoherence extends CoherencePolicy {
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))
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}
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def newProbeReply (incoming: ProbeRequest, state: UFix): ProbeReply = {
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val reply = Wire() { new ProbeReply() }
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val with_data = MuxLookup(incoming.p_type, state, Array(
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probeInvalidate -> P_REP_INVALIDATE_DATA,
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probeDowngrade -> P_REP_DOWNGRADE_DATA,
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probeCopy -> P_REP_COPY_DATA
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))
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val without_data = MuxLookup(incoming.p_type, state, Array(
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probeInvalidate -> P_REP_INVALIDATE_ACK,
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probeDowngrade -> P_REP_DOWNGRADE_ACK,
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probeCopy -> P_REP_COPY_ACK
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))
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reply.p_type := Mux(needsWriteback(state), with_data, without_data)
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reply.global_xact_id := incoming.global_xact_id
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reply
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}
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def probeReplyHasData (reply: ProbeReply): Bool = {
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(reply.p_type === P_REP_INVALIDATE_DATA ||
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reply.p_type === P_REP_DOWNGRADE_DATA ||
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@ -446,6 +468,9 @@ class CoherenceHubNull extends CoherenceHub {
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io.tiles(0).xact_abort.valid := Bool(false)
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io.tiles(0).xact_finish.ready := Bool(true)
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io.tiles(0).probe_req.valid := Bool(false)
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io.tiles(0).probe_rep.ready := Bool(true)
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io.tiles(0).probe_rep_data.ready := Bool(true)
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}
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@ -188,6 +188,8 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
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val mem_rep = (new ioPipe) { new TransactionReply }.flip
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val mem_finish = (new ioDecoupled) { new TransactionFinish }
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val wb_req = (new ioDecoupled) { new WritebackReq }
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val probe_writeback = (new ioDecoupled) { Bool() }.flip
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val probe_refill = (new ioDecoupled) { Bool() }.flip
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}
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val s_invalid :: s_wb_req :: s_wb_resp :: s_refill_req :: s_refill_resp :: s_drain_rpq :: Nil = Enum(6) { UFix() }
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@ -238,6 +240,8 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
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when (abort) { state := s_wb_req }
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}
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when (state === s_wb_req && io.wb_req.ready) {
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when (io.probe_writeback.valid && idx_match) { state := s_refill_req }
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when (io.wb_req.ready) { state := s_wb_resp }
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state := s_wb_resp
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}
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@ -277,6 +281,9 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
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io.wb_req.bits.way_oh := req.way_oh
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io.wb_req.bits.tile_xact_id := Bits(id)
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io.probe_writeback.ready := (state != s_wb_resp) || !idx_match
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io.probe_refill.ready := (state != s_refill_resp) || !idx_match
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io.mem_req.valid := (state === s_refill_req) && !flush
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io.mem_req.bits.t_type := xact_type
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io.mem_req.bits.address := Cat(req.tag, req.idx).toUFix
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@ -307,6 +314,7 @@ class MSHRFile extends Component {
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val mem_rep = (new ioPipe) { new TransactionReply }.flip
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val mem_finish = (new ioDecoupled) { new TransactionFinish }
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val wb_req = (new ioDecoupled) { new WritebackReq }
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val probe = (new ioDecoupled) { Bool() }.flip
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val cpu_resp_val = Bool(OUTPUT)
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val cpu_resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT)
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@ -322,6 +330,7 @@ class MSHRFile extends Component {
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sdq.setTarget('inst)
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val tag_mux = (new Mux1H(NMSHR)){ Bits(width = TAG_BITS) }
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val wb_probe_mux = (new Mux1H(NMSHR)) { new WritebackReq }
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val mem_resp_mux = (new Mux1H(NMSHR)){ new DataArrayArrayReq }
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val meta_req_arb = (new Arbiter(NMSHR)) { new MetaArrayArrayReq() }
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val mem_req_arb = (new Arbiter(NMSHR)) { new TransactionInit }
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@ -331,17 +340,22 @@ class MSHRFile extends Component {
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val alloc_arb = (new Arbiter(NMSHR)) { Bool() }
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val tag_match = tag_mux.io.out === io.req.bits.tag
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val wb_probe_match = wb_probe_mux.io.out.tag === io.req.bits.tag
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var idx_match = Bool(false)
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var pri_rdy = Bool(false)
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var fence = Bool(false)
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var sec_rdy = Bool(false)
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var writeback_probe_rdy = Bool(true)
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var refill_probe_rdy = Bool(true)
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for (i <- 0 to NMSHR-1) {
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val mshr = new MSHR(i)
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tag_mux.io.sel(i) := mshr.io.idx_match
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tag_mux.io.in(i) := mshr.io.tag
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wb_probe_mux.io.sel(i) := mshr.io.idx_match
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wb_probe_mux.io.in(i) := mshr.io.wb_req.bits
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alloc_arb.io.in(i).valid := mshr.io.req_pri_rdy
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mshr.io.req_pri_val := alloc_arb.io.in(i).ready
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@ -355,6 +369,8 @@ class MSHRFile extends Component {
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mshr.io.mem_finish <> mem_finish_arb.io.in(i)
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mshr.io.wb_req <> wb_req_arb.io.in(i)
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mshr.io.replay <> replay_arb.io.in(i)
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mshr.io.probe_refill.valid := io.probe.valid && tag_match
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mshr.io.probe_writeback.valid := io.probe.valid && wb_probe_match
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mshr.io.mem_abort <> io.mem_abort
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mshr.io.mem_rep <> io.mem_rep
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@ -367,6 +383,8 @@ class MSHRFile extends Component {
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sec_rdy = sec_rdy || mshr.io.req_sec_rdy
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fence = fence || !mshr.io.req_pri_rdy
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idx_match = idx_match || mshr.io.idx_match
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refill_probe_rdy = refill_probe_rdy && mshr.io.probe_refill.ready
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writeback_probe_rdy = writeback_probe_rdy && mshr.io.probe_writeback.ready
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}
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alloc_arb.io.out.ready := io.req.valid && sdq_rdy && !idx_match
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@ -382,6 +400,7 @@ class MSHRFile extends Component {
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io.mem_resp_offset := mem_resp_mux.io.out.inner_req.offset
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io.mem_resp_way_oh := mem_resp_mux.io.out.way_en
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io.fence_rdy := !fence
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io.probe.ready := (refill_probe_rdy || !tag_match) && (writeback_probe_rdy || !wb_probe_match)
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val replay = Queue(replay_arb.io.out, 1, pipe = true)
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replay.ready := io.data_req.ready
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@ -399,19 +418,23 @@ class MSHRFile extends Component {
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class WritebackUnit extends Component {
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val io = new Bundle {
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val req = (new ioDecoupled) { new WritebackReq() }.flip
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val data_req = (new ioDecoupled) { new DataArrayArrayReq() }
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val req = (new ioDecoupled) { new WritebackReq() }.flip
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val probe = (new ioDecoupled) { new WritebackReq() }.flip
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val data_req = (new ioDecoupled) { new DataArrayArrayReq() }
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val data_resp = Bits(MEM_DATA_BITS, INPUT)
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val mem_req = (new ioDecoupled) { new TransactionInit }
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val mem_req_data = (new ioDecoupled) { new TransactionInitData }
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val probe_rep_data = (new ioDecoupled) { new ProbeReplyData }
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}
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val valid = Reg(resetVal = Bool(false))
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val is_probe = Reg() { Bool() }
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val data_req_fired = Reg(resetVal = Bool(false))
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val cmd_sent = Reg() { Bool() }
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val cnt = Reg() { UFix(width = log2up(REFILL_CYCLES+1)) }
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val req = Reg() { new WritebackReq() }
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val dout_rdy = Mux(is_probe, io.probe_rep_data.ready, io.mem_req_data.ready)
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data_req_fired := Bool(false)
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when (valid && io.mem_req.ready) {
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cmd_sent := Bool(true)
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@ -420,21 +443,30 @@ class WritebackUnit extends Component {
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data_req_fired := Bool(true)
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cnt := cnt + UFix(1)
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}
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when (data_req_fired && !io.mem_req_data.ready) {
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when (data_req_fired && !dout_rdy) {
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data_req_fired := Bool(false)
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cnt := cnt - UFix(1)
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}
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when ((cnt === UFix(REFILL_CYCLES)) && io.mem_req_data.ready) {
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.elsewhen (cmd_sent && (cnt === UFix(REFILL_CYCLES))) {
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valid := Bool(false)
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}
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when (io.probe.valid && io.probe.ready) {
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valid := Bool(true)
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is_probe := Bool(true)
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cmd_sent := Bool(true)
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cnt := UFix(0)
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req := io.probe.bits
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}
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when (io.req.valid && io.req.ready) {
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valid := Bool(true)
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is_probe := Bool(false)
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cmd_sent := Bool(false)
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cnt := UFix(0)
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req := io.req.bits
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}
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io.req.ready := !valid
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io.req.ready := !valid && !io.probe.valid
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io.probe.ready := !valid
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io.data_req.valid := valid && (cnt < UFix(REFILL_CYCLES))
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io.data_req.bits.way_en := req.way_oh
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io.data_req.bits.inner_req.idx := req.idx
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@ -447,8 +479,70 @@ class WritebackUnit extends Component {
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io.mem_req.bits.t_type := X_INIT_WRITE_UNCACHED
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io.mem_req.bits.address := Cat(req.tag, req.idx).toUFix
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io.mem_req.bits.tile_xact_id := req.tile_xact_id
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io.mem_req_data.valid := data_req_fired
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io.mem_req_data.valid := data_req_fired && !is_probe
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io.mem_req_data.bits.data := io.data_resp
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io.probe_rep_data.valid := data_req_fired && is_probe
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io.probe_rep_data.bits.data := io.data_resp
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}
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class ProbeUnit extends Component with FourStateCoherence {
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val io = new Bundle {
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val req = (new ioDecoupled) { new ProbeRequest }.flip
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val rep = (new ioDecoupled) { new ProbeReply }
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val meta_req = (new ioDecoupled) { new MetaArrayArrayReq }
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val mshr_req = (new ioDecoupled) { Bool() }
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val wb_req = (new ioDecoupled) { new WritebackReq }
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val hit_way_oh = Bits(NWAYS, INPUT)
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val line_state = UFix(2, INPUT)
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val address = Bits(PADDR_BITS-OFFSET_BITS, OUTPUT)
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}
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val s_invalid :: s_meta_req :: s_meta_resp :: s_probe_rep :: s_writeback_req :: s_writeback_resp :: Nil = Enum(6) { UFix() }
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val state = Reg(resetVal = s_invalid)
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val line_state = Reg() { UFix() }
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val way_oh = Reg() { Bits() }
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val req = Reg() { new ProbeRequest() }
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when ((state === s_writeback_resp) && io.wb_req.ready) {
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state := s_invalid
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}
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when ((state === s_writeback_req) && io.wb_req.ready) {
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state := s_writeback_resp
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}
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when ((state === s_probe_rep) && io.meta_req.ready && io.rep.ready) {
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state := Mux(way_oh.orR && needsWriteback(line_state), s_writeback_req, s_invalid)
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}
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when (state === s_meta_resp) {
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way_oh := io.hit_way_oh
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line_state := io.line_state
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state := Mux(!io.mshr_req.ready, s_meta_req, s_probe_rep)
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}
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when ((state === s_meta_req) && io.meta_req.ready) {
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state := s_meta_resp
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}
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when ((state === s_invalid) && io.req.valid) {
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state := s_meta_req
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req := io.req.bits
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}
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io.req.ready := state === s_invalid
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io.rep.valid := state === s_probe_rep && io.meta_req.ready
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io.rep.bits := newProbeReply(req, line_state)
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val new_state = newStateOnProbeReq(req, line_state)
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io.meta_req.valid := state === s_meta_req || state === s_meta_resp || state === s_probe_rep && new_state != line_state
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io.meta_req.bits.way_en := Mux(state === s_probe_rep, way_oh, ~UFix(0, NWAYS))
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io.meta_req.bits.inner_req.rw := state === s_probe_rep
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io.meta_req.bits.inner_req.idx := req.address
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io.meta_req.bits.inner_req.data.state := new_state
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io.meta_req.bits.inner_req.data.tag := req.address >> UFix(OFFSET_BITS)
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io.mshr_req.valid := state === s_meta_resp
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io.address := req.address
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io.wb_req.valid := state === s_writeback_req
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io.wb_req.bits.way_oh := way_oh
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io.wb_req.bits.idx := req.address
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io.wb_req.bits.tag := req.address >> UFix(OFFSET_BITS)
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}
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class FlushUnit(lines: Int) extends Component with FourStateCoherence{
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@ -716,11 +810,13 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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val r_req_readwrite = r_req_read || r_req_write || r_req_prefetch
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val nack_hit = Wire() { Bool() }
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val wb = new WritebackUnit
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val prober = new ProbeUnit
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val mshr = new MSHRFile()
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val flusher = new FlushUnit(lines)
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val replay_amo_val = mshr.io.data_req.valid && mshr.io.data_req.bits.cmd(3).toBool
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// reset and flush unit
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val flusher = new FlushUnit(lines)
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val flushed = Reg(resetVal = Bool(true))
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flushed := flushed && (!r_cpu_req_val || r_req_flush) || r_cpu_req_val && r_req_flush && mshr.io.fence_rdy && flusher.io.req.ready
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flusher.io.req.valid := r_cpu_req_val && r_req_flush && mshr.io.fence_rdy && !flushed
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@ -756,7 +852,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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// tags
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val meta = new MetaDataArrayArray(lines)
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val meta_arb = (new Arbiter(3)) { new MetaArrayArrayReq() }
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val meta_arb = (new Arbiter(4)) { new MetaArrayArrayReq() }
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flusher.io.meta_req <> meta_arb.io.in(0)
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meta_arb.io.out <> meta.io.req
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@ -766,14 +862,13 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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data_arb.io.out <> data.io.req
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// cpu tag check
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meta_arb.io.in(2).valid := io.cpu.req_val
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meta_arb.io.in(2).bits.inner_req.idx := io.cpu.req_idx(indexmsb,indexlsb)
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meta_arb.io.in(2).bits.inner_req.rw := Bool(false)
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meta_arb.io.in(2).bits.inner_req.data.state := UFix(0) // don't care
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meta_arb.io.in(2).bits.inner_req.data.tag := UFix(0) // don't care
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meta_arb.io.in(2).bits.way_en := ~UFix(0, NWAYS)
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val early_tag_nack = !meta_arb.io.in(2).ready
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val cpu_req_tag = Cat(io.cpu.req_ppn, r_cpu_req_idx)(tagmsb,taglsb)
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meta_arb.io.in(3).valid := io.cpu.req_val
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meta_arb.io.in(3).bits.inner_req.idx := io.cpu.req_idx(indexmsb,indexlsb)
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meta_arb.io.in(3).bits.inner_req.rw := Bool(false)
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meta_arb.io.in(3).bits.way_en := ~UFix(0, NWAYS)
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val early_tag_nack = !meta_arb.io.in(3).ready
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val cpu_req_ppn = Mux(prober.io.mshr_req.valid, prober.io.address >> UFix(PGIDX_BITS-OFFSET_BITS), io.cpu.req_ppn)
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val cpu_req_tag = Cat(cpu_req_ppn, r_cpu_req_idx)(tagmsb,taglsb)
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val tag_match_arr = (0 until NWAYS).map( w => isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
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val tag_match = Cat(Bits(0),tag_match_arr:_*).orR
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val tag_match_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec
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@ -785,10 +880,19 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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val data_resp_mux = Mux1H(data_resp_way_oh, data.io.resp)
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// writeback unit
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val wb = new WritebackUnit
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wb.io.req <> mshr.io.wb_req
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wb.io.data_req <> data_arb.io.in(3)
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wb.io.data_resp <> data_resp_mux
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wb.io.probe_rep_data <> io.mem.probe_rep_data
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// probes
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prober.io.req <> io.mem.probe_req
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prober.io.rep <> io.mem.probe_rep
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prober.io.meta_req <> meta_arb.io.in(2)
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prober.io.mshr_req <> mshr.io.probe
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prober.io.wb_req <> wb.io.probe
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prober.io.hit_way_oh := hit_way_oh
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prober.io.line_state := meta_resp_mux.state
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// replacement policy
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val replacer = new RandomReplacementWayGen()
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@ -820,7 +924,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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val p_store_idx_match = p_store_valid && (r_cpu_req_idx(indexmsb,indexlsb) === p_store_idx(indexmsb,indexlsb))
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val p_store_offset_match = (r_cpu_req_idx(indexlsb-1,offsetlsb) === p_store_idx(indexlsb-1,offsetlsb))
|
||||
val p_store_match = r_cpu_req_val_ && r_req_read && p_store_idx_match && p_store_offset_match
|
||||
val drain_store_val = (p_store_valid && (!io.cpu.req_val || !req_read || Reg(wb.io.req.valid || mshr.io.data_req.valid))) || p_store_match
|
||||
val drain_store_val = (p_store_valid && (!io.cpu.req_val || !req_read || wb.io.data_req.valid || mshr.io.data_req.valid)) || p_store_match
|
||||
data_arb.io.in(2).bits.inner_req.offset := p_store_idx(offsetmsb,ramindexlsb)
|
||||
data_arb.io.in(2).bits.inner_req.idx := p_store_idx(indexmsb,indexlsb)
|
||||
data_arb.io.in(2).bits.inner_req.rw := Bool(true)
|
||||
|
|
@ -857,7 +961,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
|
|||
// miss handling
|
||||
mshr.io.req.valid := r_cpu_req_val && r_req_readwrite && !nack_hit || flusher.io.mshr_req.valid
|
||||
mshr.io.req.bits.tag_miss := !tag_hit || flusher.io.mshr_req.valid
|
||||
mshr.io.req.bits.old_dirty := needsWriteback(meta_wb_mux.state) && !tag_match // don't wb upgrades
|
||||
mshr.io.req.bits.old_dirty := needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades
|
||||
mshr.io.req.bits.old_tag := meta_wb_mux.tag
|
||||
mshr.io.req.bits.tag := cpu_req_tag
|
||||
mshr.io.req.bits.idx := r_cpu_req_idx(indexmsb,indexlsb)
|
||||
|
|
@ -876,7 +980,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
|
|||
|
||||
// replays
|
||||
val replay = mshr.io.data_req.bits
|
||||
val stall_replay = r_replay_amo || p_amo || p_store_valid || flusher.io.meta_req.valid
|
||||
val stall_replay = r_replay_amo || p_amo || flusher.io.meta_req.valid || p_store_valid
|
||||
val replay_val = mshr.io.data_req.valid
|
||||
val replay_fire = replay_val && !stall_replay
|
||||
val replay_rdy = data_arb.io.in(1).ready && !stall_replay
|
||||
|
|
@ -940,7 +1044,9 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
|
|||
|
||||
val xact_init_arb = (new Arbiter(2)) { new TransactionInit }
|
||||
xact_init_arb.io.in(0) <> wb.io.mem_req
|
||||
xact_init_arb.io.in(1) <> mshr.io.mem_req
|
||||
xact_init_arb.io.in(1).valid := mshr.io.mem_req.valid && prober.io.req.ready
|
||||
mshr.io.mem_req.ready := xact_init_arb.io.in(1).ready && prober.io.req.ready
|
||||
xact_init_arb.io.in(1).bits := mshr.io.mem_req.bits
|
||||
io.mem.xact_init <> xact_init_arb.io.out
|
||||
|
||||
io.mem.xact_init_data <> wb.io.mem_req_data
|
||||
|
|
|
|||
|
|
@ -32,6 +32,9 @@ class Top() extends Component {
|
|||
arbiter.io.mem.xact_abort <> Queue(hub.io.tiles(0).xact_abort)
|
||||
arbiter.io.mem.xact_rep <> Pipe(hub.io.tiles(0).xact_rep)
|
||||
hub.io.tiles(0).xact_finish <> Queue(arbiter.io.mem.xact_finish)
|
||||
dcache.io.mem.probe_req <> Queue(hub.io.tiles(0).probe_req)
|
||||
hub.io.tiles(0).probe_rep <> Queue(dcache.io.mem.probe_rep, 1)
|
||||
hub.io.tiles(0).probe_rep_data <> Queue(dcache.io.mem.probe_rep_data)
|
||||
// connect hub to memory
|
||||
io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
|
||||
io.mem.req_data <> Queue(hub.io.mem.req_data)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user