fix D$ store-upgrade bug
loads to the same address as stores that cause an upgrade could return the old value
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4f4b990a4f
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8ffdac9526
@ -7,7 +7,7 @@ object Constants
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{
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val HAVE_RVC = false
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val HAVE_FPU = true
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val HAVE_VEC = true
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val HAVE_VEC = false
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val BR_N = UFix(0, 4);
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val BR_EQ = UFix(1, 4);
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@ -292,6 +292,7 @@ class MSHR(id: Int) extends Component with FourStateCoherence {
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class MSHRFile extends Component {
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val io = new Bundle {
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val req = (new ioDecoupled) { new MSHRReq }.flip
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val secondary_miss = Bool(OUTPUT)
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val mem_resp_idx = Bits(IDX_BITS, OUTPUT)
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val mem_resp_offset = Bits(log2up(REFILL_CYCLES), OUTPUT)
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@ -376,6 +377,7 @@ class MSHRFile extends Component {
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wb_req_arb.io.out <> io.wb_req
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io.req.ready := Mux(idx_match, tag_match && sec_rdy, pri_rdy) && sdq_rdy
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io.secondary_miss := idx_match
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io.mem_resp_idx := mem_resp_mux.io.out.inner_req.idx
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io.mem_resp_offset := mem_resp_mux.io.out.inner_req.offset
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io.mem_resp_way_oh := mem_resp_mux.io.out.way_en
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@ -930,9 +932,9 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence {
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io.cpu.req_rdy := flusher.io.req.ready && !(r_cpu_req_val_ && r_req_flush) && !pending_fence
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io.cpu.resp_nack := r_cpu_req_val_ && !io.cpu.req_kill && nack
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io.cpu.resp_val := (tag_hit && !nack && r_req_read) || mshr.io.cpu_resp_val
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io.cpu.resp_val := (tag_hit && !mshr.io.secondary_miss && !nack && r_req_read) || mshr.io.cpu_resp_val
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io.cpu.resp_replay := mshr.io.cpu_resp_val
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io.cpu.resp_miss := r_cpu_req_val_ && !tag_match && r_req_read
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io.cpu.resp_miss := r_cpu_req_val_ && (!tag_match || mshr.io.secondary_miss) && r_req_read
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io.cpu.resp_tag := Mux(mshr.io.cpu_resp_val, mshr.io.cpu_resp_tag, r_cpu_req_tag)
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io.cpu.resp_type := loadgen.io.typ
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io.cpu.resp_data := loadgen.io.dout
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@ -26,7 +26,7 @@ class Top() extends Component {
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arbiter.io.requestor(1) <> icache_pf.io.mem
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arbiter.io.requestor(2) <> htif.io.mem
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val hub = new CoherenceHubNull
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val hub = new CoherenceHubBroadcast
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// connect tile to hub
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hub.io.tiles(0).xact_init <> Queue(arbiter.io.mem.xact_init)
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arbiter.io.mem.xact_abort <> Queue(hub.io.tiles(0).xact_abort)
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