riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

reduce HTIF width

Browse Source
This commit is contained in:
Andrew Waterman 2012-03-25 23:49:59 -07:00
parent ef505de017
commit 5f53cd4ac1
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/consts.scala
View File

@ -7,7 +7,7 @@ object Constants
{
val HAVE_RVC = false
val HAVE_FPU = true
val HAVE_VEC = true
val HAVE_VEC = false
val BR_N = UFix(0, 4);
val BR_EQ = UFix(1, 4);