pipeline LLC further
This commit is contained in:
Andrew Waterman
parent
3a8f3e0de5
commit
def913096e
@ -4,14 +4,17 @@ import Chisel._
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import Node._
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import Constants._
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class BigMem[T <: Data](n: Int, readLatency: Int, leaf: Mem[Bits])(gen: => T) extends Component
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class BigMem[T <: Data](n: Int, preLatency: Int, postLatency: Int, leaf: Mem[Bits])(gen: => T) extends Component
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{
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val io = new Bundle {
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class Inputs extends Bundle {
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val addr = UFix(INPUT, log2Up(n))
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val en = Bool(INPUT)
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val rw = Bool(INPUT)
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val wdata = gen.asInput
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val wmask = gen.asInput
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override def clone = new Inputs().asInstanceOf[this.type]
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}
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val io = new Bundle {
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val in = new PipeIO()(new Inputs).flip
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val rdata = gen.asOutput
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}
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val data = gen
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@ -21,63 +24,52 @@ class BigMem[T <: Data](n: Int, readLatency: Int, leaf: Mem[Bits])(gen: => T) ex
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if (nDeep > 1 || colMux > 1)
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require(isPow2(n) && isPow2(leaf.n))
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val idx = io.addr(log2Up(n/nDeep/colMux)-1, 0)
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val rdataDeep = Vec(nDeep) { Bits() }
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val rdataSel = Vec(nDeep) { Bool() }
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val cond = Vec(nDeep) { Bool() }
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val ren = Vec(nDeep) { Bool() }
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val reg_ren = Vec(nDeep) { Reg() { Bool() } }
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val renOut = Vec(nDeep) { Bool() }
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val raddrOut = Vec(nDeep) { UFix() }
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val rdata = Vec(nDeep) { Vec(nWide) { Bits() } }
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val wdata = io.wdata.toBits
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val wmask = io.wmask.toBits
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for (i <- 0 until nDeep) {
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cond(i) := (if (nDeep == 1) io.en else io.en && UFix(i) === io.addr(log2Up(n)-1, log2Up(n/nDeep)))
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ren(i) := cond(i) && !io.rw
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reg_ren(i) := ren(i)
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val in = Pipe(io.in.valid && (if (nDeep == 1) Bool(true) else UFix(i) === io.in.bits.addr(log2Up(n)-1, log2Up(n/nDeep))), io.in.bits, preLatency)
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val idx = in.bits.addr(log2Up(n/nDeep/colMux)-1, 0)
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val wdata = in.bits.wdata.toBits
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val wmask = in.bits.wmask.toBits
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val ren = in.valid && !in.bits.rw
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val reg_ren = Reg(ren)
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val rdata = Vec(nWide) { Bits() }
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renOut(i) := ren(i)
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raddrOut(i) := io.addr
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if (readLatency > 0) {
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val r = Pipe(ren(i), io.addr, readLatency)
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renOut(i) := r.valid
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raddrOut(i) := r.bits
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}
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val r = Pipe(ren, in.bits.addr, postLatency)
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for (j <- 0 until nWide) {
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val mem = leaf.clone
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var dout: Bits = null
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val dout1 = if (readLatency > 0) Reg() { Bits() } else null
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val dout1 = if (postLatency > 0) Reg() { Bits() } else null
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var wmask0 = Fill(colMux, wmask(math.min(wmask.getWidth, leaf.data.width*(j+1))-1, leaf.data.width*j))
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if (colMux > 1)
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wmask0 = wmask0 & FillInterleaved(gen.width, UFixToOH(io.addr(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)), log2Up(colMux)))
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wmask0 = wmask0 & FillInterleaved(gen.width, UFixToOH(in.bits.addr(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)), log2Up(colMux)))
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val wdata0 = Fill(colMux, wdata(math.min(wdata.getWidth, leaf.data.width*(j+1))-1, leaf.data.width*j))
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when (cond(i)) {
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when (io.rw) { mem.write(idx, wdata0, wmask0) }
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.otherwise { if (readLatency > 0) dout1 := mem(idx) }
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when (in.valid) {
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when (in.bits.rw) { mem.write(idx, wdata0, wmask0) }
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.otherwise { if (postLatency > 0) dout1 := mem(idx) }
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}
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if (readLatency == 0) {
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if (postLatency == 0) {
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dout = mem(idx)
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} else if (readLatency == 1) {
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} else if (postLatency == 1) {
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dout = dout1
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} else
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dout = Pipe(reg_ren(i), dout1, readLatency-1).bits
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dout = Pipe(reg_ren, dout1, postLatency-1).bits
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rdata(i)(j) := dout
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rdata(j) := dout
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}
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val rdataWide = rdata(i).reduceLeft((x, y) => Cat(y, x))
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val rdataWide = rdata.reduceLeft((x, y) => Cat(y, x))
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var colMuxOut = rdataWide
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if (colMux > 1) {
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val colMuxIn = Vec((0 until colMux).map(k => rdataWide(gen.width*(k+1)-1, gen.width*k))) { Bits() }
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colMuxOut = colMuxIn(raddrOut(i)(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)))
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colMuxOut = colMuxIn(r.bits(log2Up(n/nDeep)-1, log2Up(n/nDeep/colMux)))
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}
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rdataDeep(i) := colMuxOut
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rdataSel(i) := renOut(i)
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rdataSel(i) := r.valid
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}
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io.rdata := Mux1H(rdataSel, rdataDeep)
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@ -247,7 +239,7 @@ class LLCData(latency: Int, sets: Int, ways: Int, leaf: Mem[Bits]) extends Compo
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val mem_resp_way = UFix(INPUT, log2Up(ways))
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}
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val data = new BigMem(sets*ways*REFILL_CYCLES, latency, leaf)(Bits(width = MEM_DATA_BITS))
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val data = new BigMem(sets*ways*REFILL_CYCLES, 1, latency-1, leaf)(Bits(width = MEM_DATA_BITS))
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class QEntry extends MemResp {
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val isWriteback = Bool()
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override def clone = new QEntry().asInstanceOf[this.type]
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@ -259,31 +251,31 @@ class LLCData(latency: Int, sets: Int, ways: Int, leaf: Mem[Bits]) extends Compo
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val count = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
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val refillCount = Reg(resetVal = UFix(0, log2Up(REFILL_CYCLES)))
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when (data.io.en && !io.mem_resp.valid) {
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when (data.io.in.valid && !io.mem_resp.valid) {
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count := count + UFix(1)
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when (valid && count === UFix(REFILL_CYCLES-1)) { valid := Bool(false) }
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}
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when (io.req.valid && io.req.ready) { valid := Bool(true); req := io.req.bits }
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when (io.mem_resp.valid) { refillCount := refillCount + UFix(1) }
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data.io.en := io.req.valid && io.req.ready && Mux(io.req.bits.rw, io.req_data.valid, qReady)
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data.io.addr := Cat(io.req.bits.way, io.req.bits.addr(log2Up(sets)-1, 0), count).toUFix
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data.io.rw := io.req.bits.rw
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data.io.wdata := io.req_data.bits.data
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data.io.wmask := Fix(-1, io.req_data.bits.data.width)
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data.io.in.valid := io.req.valid && io.req.ready && Mux(io.req.bits.rw, io.req_data.valid, qReady)
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data.io.in.bits.addr := Cat(io.req.bits.way, io.req.bits.addr(log2Up(sets)-1, 0), count).toUFix
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data.io.in.bits.rw := io.req.bits.rw
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data.io.in.bits.wdata := io.req_data.bits.data
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data.io.in.bits.wmask := Fix(-1, io.req_data.bits.data.width)
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when (valid) {
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data.io.en := Mux(req.rw, io.req_data.valid, qReady)
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data.io.addr := Cat(req.way, req.addr(log2Up(sets)-1, 0), count).toUFix
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data.io.rw := req.rw
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data.io.in.valid := Mux(req.rw, io.req_data.valid, qReady)
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data.io.in.bits.addr := Cat(req.way, req.addr(log2Up(sets)-1, 0), count).toUFix
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data.io.in.bits.rw := req.rw
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}
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when (io.mem_resp.valid) {
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data.io.en := Bool(true)
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data.io.addr := Cat(io.mem_resp_way, io.mem_resp_set, refillCount).toUFix
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data.io.rw := Bool(true)
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data.io.wdata := io.mem_resp.bits.data
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data.io.in.valid := Bool(true)
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data.io.in.bits.addr := Cat(io.mem_resp_way, io.mem_resp_set, refillCount).toUFix
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data.io.in.bits.rw := Bool(true)
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data.io.in.bits.wdata := io.mem_resp.bits.data
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}
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val tagPipe = Pipe(data.io.en && !data.io.rw, Mux(valid, req.tag, io.req.bits.tag), latency)
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val tagPipe = Pipe(data.io.in.valid && !data.io.in.bits.rw, Mux(valid, req.tag, io.req.bits.tag), latency)
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q.io.enq.valid := tagPipe.valid
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q.io.enq.bits.tag := tagPipe.bits
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q.io.enq.bits.isWriteback := Pipe(Mux(valid, req.isWriteback, io.req.bits.isWriteback), Bool(false), latency).valid
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@ -358,8 +350,8 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[Bits], da
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val memCmdArb = (new Arbiter(2)) { new MemReqCmd }
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val dataArb = (new Arbiter(2)) { new LLCDataReq(ways) }
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val mshr = new LLCMSHRFile(sets, ways, outstanding)
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val tags = new BigMem(sets, 1, tagLeaf)(Bits(width = metaWidth*ways))
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val data = new LLCData(3, sets, ways, dataLeaf)
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val tags = new BigMem(sets, 0, 1, tagLeaf)(Bits(width = metaWidth*ways))
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val data = new LLCData(4, sets, ways, dataLeaf)
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val writeback = new LLCWriteback(2)
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val initCount = Reg(resetVal = UFix(0, log2Up(sets+1)))
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@ -392,11 +384,11 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[Bits], da
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val setDirty = s2_valid && s2.rw && s2_hit && !s2_hit_dirty
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stall_s1 := initialize || mshr.io.tag.valid || setDirty || s2_valid && !s2_hit || stall_s2
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tags.io.en := (io.cpu.req_cmd.valid || replay_s1) && !stall_s1 || initialize || setDirty || mshr.io.tag.valid
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tags.io.addr := Mux(initialize, initCount, Mux(setDirty, s2.addr, Mux(mshr.io.tag.valid, mshr.io.tag.bits.addr, Mux(replay_s1, s1.addr, io.cpu.req_cmd.bits.addr)))(log2Up(sets)-1,0))
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tags.io.rw := initialize || setDirty || mshr.io.tag.valid
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tags.io.wdata := Mux(initialize, UFix(0), Fill(ways, Cat(setDirty, Bool(true), Mux(setDirty, s2.addr, mshr.io.tag.bits.addr)(mshr.io.tag.bits.addr.width-1, mshr.io.tag.bits.addr.width-tagWidth))))
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tags.io.wmask := FillInterleaved(metaWidth, Mux(initialize, Fix(-1, ways), UFixToOH(Mux(setDirty, s2_hit_way, mshr.io.tag.bits.way))))
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tags.io.in.valid := (io.cpu.req_cmd.valid || replay_s1) && !stall_s1 || initialize || setDirty || mshr.io.tag.valid
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tags.io.in.bits.addr := Mux(initialize, initCount, Mux(setDirty, s2.addr, Mux(mshr.io.tag.valid, mshr.io.tag.bits.addr, Mux(replay_s1, s1.addr, io.cpu.req_cmd.bits.addr)))(log2Up(sets)-1,0))
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tags.io.in.bits.rw := initialize || setDirty || mshr.io.tag.valid
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tags.io.in.bits.wdata := Mux(initialize, UFix(0), Fill(ways, Cat(setDirty, Bool(true), Mux(setDirty, s2.addr, mshr.io.tag.bits.addr)(mshr.io.tag.bits.addr.width-1, mshr.io.tag.bits.addr.width-tagWidth))))
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tags.io.in.bits.wmask := FillInterleaved(metaWidth, Mux(initialize, Fix(-1, ways), UFixToOH(Mux(setDirty, s2_hit_way, mshr.io.tag.bits.way))))
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mshr.io.cpu.valid := s2_valid && !s2_hit && !s2.rw
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mshr.io.cpu.bits := s2
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@ -74,37 +74,35 @@ object Queue
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}
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}
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class pipereg[T <: Data]()(data: => T) extends Component
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class pipereg[T <: Data](latency: Int = 1)(data: => T) extends Component
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{
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val io = new Bundle {
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val enq = new PipeIO()(data).flip
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val deq = new PipeIO()(data)
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}
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//val bits = Reg() { io.enq.bits.clone }
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//when (io.enq.valid) {
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// bits := io.enq.bits
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//}
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var bits: T = io.enq.bits
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var valid: Bool = io.enq.valid
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val r = Reg() { io.enq.bits.clone }
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when (io.enq.valid) { r := io.enq.bits }
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for (i <- 0 until latency) {
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val reg_bits = Reg() { io.enq.bits.clone }
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val reg_valid = Reg(valid, resetVal = Bool(false))
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when (valid) { reg_bits := bits }
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valid = reg_valid
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bits = reg_bits
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}
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io.deq.valid := Reg(io.enq.valid, resetVal = Bool(false))
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io.deq.bits <> r
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io.deq.valid := valid
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io.deq.bits := bits
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}
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object Pipe
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{
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def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): PipeIO[T] = {
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val q = (new pipereg) { enqBits.clone }
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val q = (new pipereg(latency)) { enqBits.clone }
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q.io.enq.valid := enqValid
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q.io.enq.bits := enqBits
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q.io.deq
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if (latency > 1)
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Pipe(q.io.deq, latency-1)
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else
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q.io.deq
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}
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def apply[T <: Data](enqValid: Bool, enqBits: T): PipeIO[T] = apply(enqValid, enqBits, 1)
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def apply[T <: Data](enq: PipeIO[T], latency: Int = 1): PipeIO[T] = apply(enq.valid, enq.bits, latency)
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