riscv/rocket-chip
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fix signedness of zero fmul results

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We were using the FMA unit to compute rs1 * rs2 + 0.0 for fmul,
which incorrectly computes +0.0 when rs1 * rs2 == -0.0.  Now we
add -0.0 if rs1*rs2 is negative.
This commit is contained in:
Andrew Waterman 2012-03-10 00:21:51 -08:00
parent e3a68848e0
commit 7eb73c325e
1 changed files with 10 additions and 4 deletions
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14
rocket/src/main/scala/fpu.scala
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@ -390,12 +390,15 @@ class rocketFPUSFMAPipe(latency: Int) extends Component
io.cmd === FCMD_NMADD || io.cmd === FCMD_NMSUB
val cmd_addsub = io.cmd === FCMD_ADD || io.cmd === FCMD_SUB
val one = Bits("h80000000")
val zero = Cat(io.in1(32) ^ io.in2(32), Bits(0, 32))
when (io.valid) {
cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0))
rm := io.rm
in1 := io.in1
in2 := Mux(cmd_addsub, Bits("h80000000"), io.in2)
in3 := Mux(cmd_fma, io.in3, Mux(cmd_addsub, io.in2, Bits(0)))
in2 := Mux(cmd_addsub, one, io.in2)
in3 := Mux(cmd_fma, io.in3, Mux(cmd_addsub, io.in2, zero))
}
val fma = new hardfloat.mulAddSubRecodedFloat32_1
@ -423,12 +426,15 @@ class rocketFPUDFMAPipe(latency: Int) extends Component
io.cmd === FCMD_NMADD || io.cmd === FCMD_NMSUB
val cmd_addsub = io.cmd === FCMD_ADD || io.cmd === FCMD_SUB
val one = Bits("h8000000000000000")
val zero = Cat(io.in1(64) ^ io.in2(64), Bits(0, 64))
when (io.valid) {
cmd := Cat(io.cmd(1) & (cmd_fma || cmd_addsub), io.cmd(0))
rm := io.rm
in1 := io.in1
in2 := Mux(cmd_addsub, Bits("h8000000000000000"), io.in2)
in3 := Mux(cmd_fma, io.in3, Mux(cmd_addsub, io.in2, Bits(0)))
in2 := Mux(cmd_addsub, one, io.in2)
in3 := Mux(cmd_fma, io.in3, Mux(cmd_addsub, io.in2, zero))
}
val fma = new hardfloat.mulAddSubRecodedFloat64_1