riscv/rocket-chip
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no dessert tonight :(

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This commit is contained in:
Andrew Waterman 2012-03-26 23:50:09 -07:00
parent a70f0414fa
commit 6bda8674bd
3 changed files with 34 additions and 31 deletions
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2
rocket/src/main/scala/consts.scala
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@ -9,6 +9,8 @@ object Constants
val HAVE_FPU = true
val HAVE_VEC = true
val MEM_BACKUP_WIDTH = 16
val BR_N = UFix(0, 4);
val BR_EQ = UFix(1, 4);
val BR_NE = UFix(2, 4);

46
rocket/src/main/scala/memserdes.scala
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@ -5,17 +5,17 @@ import Node._
import Constants._
import scala.math._
class ioMemSerialized(w: Int) extends Bundle
class ioMemSerialized extends Bundle
{
val req = (new ioDecoupled) { Bits(width = w) }
val resp = (new ioPipe) { Bits(width = w) }.flip
val req = (new ioDecoupled) { Bits(width = MEM_BACKUP_WIDTH) }
val resp = (new ioPipe) { Bits(width = MEM_BACKUP_WIDTH) }.flip
}
class MemSerdes(w: Int) extends Component
class MemSerdes extends Component
{
val io = new Bundle {
val wide = new ioMem().flip
val narrow = new ioMemSerialized(w)
val narrow = new ioMemSerialized
}
val abits = io.wide.req_cmd.bits.toBits.getWidth
val dbits = io.wide.req_data.bits.toBits.getWidth
@ -26,14 +26,14 @@ class MemSerdes(w: Int) extends Component
val s_idle :: s_read_addr :: s_write_addr :: s_write_idle :: s_write_data :: Nil = Enum(5) { UFix() }
val state = Reg(resetVal = s_idle)
val send_cnt = Reg(resetVal = UFix(0, log2up((max(abits, dbits)+w-1)/w)))
val send_cnt = Reg(resetVal = UFix(0, log2up((max(abits, dbits)+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)))
val data_send_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
val adone = io.narrow.req.ready && send_cnt === UFix((abits-1)/w)
val ddone = io.narrow.req.ready && send_cnt === UFix((dbits-1)/w)
val adone = io.narrow.req.ready && send_cnt === UFix((abits-1)/MEM_BACKUP_WIDTH)
val ddone = io.narrow.req.ready && send_cnt === UFix((dbits-1)/MEM_BACKUP_WIDTH)
when (io.narrow.req.valid && io.narrow.req.ready) {
send_cnt := send_cnt + UFix(1)
out_buf := out_buf >> UFix(w)
out_buf := out_buf >> UFix(MEM_BACKUP_WIDTH)
}
when (io.wide.req_cmd.valid && io.wide.req_cmd.ready) {
out_buf := io.wide.req_cmd.bits.toBits
@ -67,19 +67,19 @@ class MemSerdes(w: Int) extends Component
send_cnt := UFix(0)
}
val recv_cnt = Reg(resetVal = UFix(0, log2up((rbits+w-1)/w)))
val recv_cnt = Reg(resetVal = UFix(0, log2up((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)))
val data_recv_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
val resp_val = Reg(resetVal = Bool(false))
resp_val := Bool(false)
when (io.narrow.resp.valid) {
recv_cnt := recv_cnt + UFix(1)
when (recv_cnt === UFix((rbits-1)/w)) {
when (recv_cnt === UFix((rbits-1)/MEM_BACKUP_WIDTH)) {
recv_cnt := UFix(0)
data_recv_cnt := data_recv_cnt + UFix(1)
resp_val := Bool(true)
}
in_buf := Cat(io.narrow.resp.bits, in_buf((rbits+w-1)/w*w-1,w))
in_buf := Cat(io.narrow.resp.bits, in_buf((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH*MEM_BACKUP_WIDTH-1,MEM_BACKUP_WIDTH))
}
io.wide.resp.valid := resp_val
@ -87,10 +87,10 @@ class MemSerdes(w: Int) extends Component
io.wide.resp.bits.data := in_buf >> UFix(io.wide.resp.bits.tag.width)
}
class MemDessert(w: Int) extends Component // test rig side
class MemDessert extends Component // test rig side
{
val io = new Bundle {
val narrow = new ioMemSerialized(w).flip
val narrow = new ioMemSerialized().flip
val wide = new ioMem
}
val abits = io.wide.req_cmd.bits.toBits.getWidth
@ -98,11 +98,11 @@ class MemDessert(w: Int) extends Component // test rig side
val rbits = io.wide.resp.bits.getWidth
require(dbits >= abits && rbits >= dbits)
val recv_cnt = Reg(resetVal = UFix(0, log2up((rbits+w-1)/w)))
val recv_cnt = Reg(resetVal = UFix(0, log2up((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)))
val data_recv_cnt = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
val adone = io.narrow.req.valid && recv_cnt === UFix((abits-1)/w)
val ddone = io.narrow.req.valid && recv_cnt === UFix((dbits-1)/w)
val rdone = io.narrow.resp.valid && recv_cnt === UFix((rbits-1)/w)
val adone = io.narrow.req.valid && recv_cnt === UFix((abits-1)/MEM_BACKUP_WIDTH)
val ddone = io.narrow.req.valid && recv_cnt === UFix((dbits-1)/MEM_BACKUP_WIDTH)
val rdone = io.narrow.resp.valid && recv_cnt === UFix((rbits-1)/MEM_BACKUP_WIDTH)
val s_cmd_recv :: s_cmd :: s_data_recv :: s_data :: s_reply :: Nil = Enum(5) { UFix() }
val state = Reg(resetVal = s_cmd_recv)
@ -110,7 +110,7 @@ class MemDessert(w: Int) extends Component // test rig side
val in_buf = Reg() { Bits() }
when (io.narrow.req.valid && io.narrow.req.ready || io.narrow.resp.valid) {
recv_cnt := recv_cnt + UFix(1)
in_buf := Cat(io.narrow.req.bits, in_buf((rbits+w-1)/w*w-1,w))
in_buf := Cat(io.narrow.req.bits, in_buf((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH*MEM_BACKUP_WIDTH-1,MEM_BACKUP_WIDTH))
}
io.narrow.req.ready := state === s_cmd_recv || state === s_data_recv
@ -140,19 +140,19 @@ class MemDessert(w: Int) extends Component // test rig side
data_recv_cnt := data_recv_cnt + UFix(1)
}
val req_cmd = in_buf >> UFix(((rbits+w-1)/w - (abits+w-1)/w)*w)
val req_cmd = in_buf >> UFix(((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH - (abits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)*MEM_BACKUP_WIDTH)
io.wide.req_cmd.valid := state === s_cmd
io.wide.req_cmd.bits.tag := req_cmd
io.wide.req_cmd.bits.addr := req_cmd.toUFix >> UFix(io.wide.req_cmd.bits.tag.width)
io.wide.req_cmd.bits.rw := req_cmd(io.wide.req_cmd.bits.tag.width + io.wide.req_cmd.bits.addr.width)
io.wide.req_data.valid := state === s_data
io.wide.req_data.bits.data := in_buf >> UFix(((rbits+w-1)/w - (dbits+w-1)/w)*w)
io.wide.req_data.bits.data := in_buf >> UFix(((rbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH - (dbits+MEM_BACKUP_WIDTH-1)/MEM_BACKUP_WIDTH)*MEM_BACKUP_WIDTH)
val dataq = (new queue(REFILL_CYCLES)) { new MemResp }
dataq.io.enq <> io.wide.resp
dataq.io.deq.ready := recv_cnt === UFix((rbits-1)/w)
dataq.io.deq.ready := recv_cnt === UFix((rbits-1)/MEM_BACKUP_WIDTH)
io.narrow.resp.valid := dataq.io.deq.valid
io.narrow.resp.bits := dataq.io.deq.bits.toBits >> (recv_cnt * UFix(w))
io.narrow.resp.bits := dataq.io.deq.bits.toBits >> (recv_cnt * UFix(MEM_BACKUP_WIDTH))
}

17
rocket/src/main/scala/top.scala
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@ -4,21 +4,21 @@ import Chisel._
import Node._;
import Constants._;
class ioTop(htif_width: Int, mem_backup_width: Int) extends Bundle {
class ioTop(htif_width: Int) extends Bundle {
val debug = new ioDebug();
val host = new ioHost(htif_width);
val host_clk = Bool(OUTPUT)
val mem_backup = new ioMemSerialized(mem_backup_width)
val mem_backup = new ioMemSerialized
val mem_backup_en = Bool(INPUT)
val mem_backup_clk = Bool(OUTPUT)
val mem = new ioMem
}
class Top() extends Component
class Top extends Component
{
val clkdiv = 32
val htif_width = 8
val mem_backup_width = 16
val io = new ioTop(htif_width, mem_backup_width);
val io = new ioTop(htif_width)
val tile = new Tile
val htif = new rocketHTIF(htif_width, 1)
@ -28,7 +28,7 @@ class Top() extends Component
hub.io.tiles(1) <> htif.io.mem
// mux between main and backup memory ports
val mem_serdes = new MemSerdes(mem_backup_width)
val mem_serdes = new MemSerdes
val mem_cmdq = (new queue(1)) { new MemReqCmd }
mem_cmdq.io.enq <> hub.io.mem.req_cmd
mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
@ -57,13 +57,14 @@ class Top() extends Component
io.host_clk := hio.io.clk_slow
// pad out the backup memory link with the HTIF divided clk
val mio = (new slowIO(clkdiv, 4)) { Bits(width = mem_backup_width) }
val mio = (new slowIO(clkdiv, 4)) { Bits(width = MEM_BACKUP_WIDTH) }
mem_serdes.io.narrow.req <> mio.io.out_fast
io.mem_backup.req <> mio.io.out_slow
mem_serdes.io.narrow.resp.valid := mio.io.in_fast.valid
mio.io.in_fast.ready := Bool(true)
mem_serdes.io.narrow.resp.bits := mio.io.in_fast.bits
io.mem_backup.resp <> mio.io.in_slow
io.mem_backup_clk := mio.io.clk_slow
tile.io.host <> htif.io.cpu(0)
io.debug <> tile.io.host.debug
@ -71,6 +72,6 @@ class Top() extends Component
object top_main {
def main(args: Array[String]) = {
chiselMain(args, () => new Top());
chiselMain(args.drop(1), () => Class.forName(args(0)).newInstance.asInstanceOf[Component])
}
}