Andrew Waterman c09eeb7fd2 fix D$ next-state logic ...

it was using the CPU command from the wrong pipeline stage,
which was a don't-care with ThreeStateIncoherence.

2012-03-07 01:42:08 -08:00

rocket/src/main/scala

fix D$ next-state logic

2012-03-07 01:42:08 -08:00

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Rocket Chip Generator (https://github.com/freechipsproject/rocket-chip)

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