fix Mux1H for bundles
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81dcb194d3
commit
6e2610b0ad
@ -158,16 +158,19 @@ class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
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val out = gen.asOutput
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}
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if (n > 2) {
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var out = io.in(0).toBits & Fill(gen.getWidth, io.sel(0))
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for (i <- 1 to n-1)
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out = out | (io.in(i).toBits & Fill(gen.getWidth, io.sel(i)))
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io.out := out
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} else if (n == 2) {
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io.out := Mux(io.sel(1), io.in(1), io.in(0))
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} else {
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io.out := io.in(0)
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def buildMux(sel: Bits, in: Vec[T], i: Int, n: Int): T = {
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if (n == 1)
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in(i)
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else
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{
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val half_n = (1 << log2up(n))/2
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val left = buildMux(sel, in, i, half_n)
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val right = buildMux(sel, in, i + half_n, n - half_n)
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Mux(sel(i+n-1,i+half_n).orR, right, left)
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}
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}
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io.out := buildMux(io.sel.toBits, io.in, 0, n)
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}
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