allow back pressure on IPI requests

rocket/src/main/scala/ctrl.scala

@@ -70,6 +70,7 @@ class ioCtrlDpath extends Bundle()
   val fp_sboard_wb_waddr = UFix(INPUT, 5);
   val irq_timer = Bool(INPUT);
   val irq_ipi   = Bool(INPUT);
+  val pcr_replay = Bool(INPUT)
 }
 
 class ioCtrlAll extends Bundle()
@@ -743,7 +744,7 @@ class rocketCtrl extends Component
   wb_reg_exception    := mem_exception && !take_pc_wb;
   wb_reg_cause        := mem_cause;
 
-  val replay_wb = wb_reg_replay || vec_replay
+  val replay_wb = wb_reg_replay || vec_replay || io.dpath.pcr_replay
 
   val wb_badvaddr_wen = wb_reg_exception && ((wb_reg_cause === UFix(10)) || (wb_reg_cause === UFix(11)))
 

rocket/src/main/scala/dpath.scala

@@ -288,6 +288,7 @@ class rocketDpath extends Component
   io.ctrl.irq_timer    := pcr.io.irq_timer;
   io.ctrl.irq_ipi      := pcr.io.irq_ipi;  
   io.ctrl.status       := pcr.io.status;
+  io.ctrl.pcr_replay   := pcr.io.replay
   io.ptbr              := pcr.io.ptbr;
   io.ptbr_wen          := pcr.io.ptbr_wen;
   

rocket/src/main/scala/dpath_util.scala

@@ -78,6 +78,7 @@ class ioDpathPCR extends Bundle()
   val ptbr_wen  = Bool(OUTPUT);
   val irq_timer = Bool(OUTPUT);
   val irq_ipi   = Bool(OUTPUT);
+  val replay    = Bool(OUTPUT)
   val vecbank   = Bits(OUTPUT, 8)
   val vecbankcnt = UFix(OUTPUT, 4)
   val vec_appvl = UFix(INPUT, 12)
@@ -175,8 +176,9 @@ class rocketDpathPCR extends Component
 
   io.irq_timer := r_irq_timer;
   io.irq_ipi := r_irq_ipi;
-  io.host.ipi.valid := Bool(false)
-  io.host.ipi.bits := wdata
+  io.host.ipi.valid := io.w.en && io.w.addr === PCR_SEND_IPI
+  io.host.ipi.bits := io.w.data
+  io.replay := io.host.ipi.valid && !io.host.ipi.ready
 
   when (wen) {
     when (waddr === PCR_STATUS) {

rocket/src/main/scala/htif.scala

@@ -209,9 +209,9 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
     for (j <- 0 until ncores) {
       when (io.cpu(j).ipi.valid && io.cpu(j).ipi.bits === UFix(i)) {
         my_ipi := Bool(true)
-        my_reset := Bool(false)
       }
     }
+    cpu.ipi.ready := Bool(true)
     when (my_ipi) {
       my_ipi := !cpu.pcr_req.ready
     }
@@ -228,7 +228,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
     }
 
     pcr_mux.io.sel(i) := me
-    pcr_mux.io.in(i) := Mux(pcr_addr === PCR_RESET, my_reset, rdata)
+    pcr_mux.io.in(i) := Mux(pcr_addr === PCR_RESET, Cat(Bits(0, 63), my_reset), rdata)
   }
 
   val tx_cmd = Mux(nack, cmd_nack, cmd_ack)