riscv/rocket-chip
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coherence mostly works now

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This commit is contained in:
Andrew Waterman 2012-04-10 02:22:45 -07:00
parent 3cdd166153
commit c0ec3794bf
4 changed files with 18 additions and 14 deletions
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1
rocket/src/main/scala/consts.scala
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@ -5,6 +5,7 @@ import scala.math._
object Constants
{
val NTILES = 1
val HAVE_RVC = false
val HAVE_FPU = true
val HAVE_VEC = true

4
rocket/src/main/scala/nbdcache.scala
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@ -826,8 +826,8 @@ class HellaCache(co: CoherencePolicy) extends Component {
(((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0))) ||
((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0)));
io.cpu.xcpt_ma_ld := r_cpu_req_val_ && r_req_read && misaligned
io.cpu.xcpt_ma_st := r_cpu_req_val_ && r_req_write && misaligned
io.cpu.xcpt_ma_ld := r_cpu_req_val_ && !early_nack && r_req_read && misaligned
io.cpu.xcpt_ma_st := r_cpu_req_val_ && !early_nack && r_req_write && misaligned
// tags
val meta = new MetaDataArrayArray(lines)

19
rocket/src/main/scala/top.scala
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@ -21,12 +21,9 @@ class Top extends Component
val io = new ioTop(htif_width)
val co = new FourStateCoherence
val tile = new Tile(co)
val htif = new rocketHTIF(htif_width, 1, co)
val hub = new CoherenceHubBroadcast(2, co)
hub.io.tiles(0) <> tile.io.tilelink
hub.io.tiles(1) <> htif.io.mem
val htif = new rocketHTIF(htif_width, NTILES, co)
val hub = new CoherenceHubBroadcast(NTILES+1, co)
hub.io.tiles(NTILES) <> htif.io.mem
// mux between main and backup memory ports
val mem_serdes = new MemSerdes
@ -67,8 +64,14 @@ class Top extends Component
io.mem_backup.resp <> mio.io.in_slow
io.mem_backup_clk := mio.io.clk_slow
tile.io.host <> htif.io.cpu(0)
io.debug <> tile.io.host.debug
var error_mode = Bool(false)
for (i <- 0 until NTILES) {
val tile = new Tile(co)
tile.io.host <> htif.io.cpu(i)
hub.io.tiles(i) <> tile.io.tilelink
error_mode = error_mode || tile.io.host.debug.error_mode
}
io.debug.error_mode := error_mode
}
object top_main {

8
rocket/src/main/scala/uncore.scala
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@ -86,11 +86,11 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
}
def doMemReqWrite(req_cmd: ioDecoupled[MemReqCmd], req_data: ioDecoupled[MemData], lock: Bool, data: ioPipe[MemData], trigger: Bool, cmd_sent: Bool, pop_data: Bits, pop_dep: Bits, at_front_of_dep_queue: Bool, tile_id: UFix) {
req_cmd.valid := !cmd_sent && at_front_of_dep_queue
req_cmd.valid := !cmd_sent && data.valid && at_front_of_dep_queue
req_cmd.bits.rw := Bool(true)
req_data.valid := data.valid && at_front_of_dep_queue
req_data.bits := data.bits
lock := at_front_of_dep_queue
lock := data.valid && at_front_of_dep_queue
when(req_cmd.ready && req_cmd.valid) {
cmd_sent := Bool(true)
}
@ -383,8 +383,8 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
val pop_p_reps = trackerList.map(_.io.pop_p_rep(j).toBool)
val do_pop = foldR(pop_p_reps)(_ || _)
p_rep.ready := Bool(true)
p_rep_data_dep_list(j).io.enq.valid := do_pop
p_rep_data_dep_list(j).io.enq.bits.global_xact_id := OHToUFix(pop_p_reps)
p_rep_data_dep_list(j).io.enq.valid := p_rep.valid && co.messageHasData(p_rep.bits)
p_rep_data_dep_list(j).io.enq.bits.global_xact_id := p_rep.bits.global_xact_id
p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data(j)))(_ || _)
when (p_rep.valid && co.messageHasData(p_rep.bits)) {
p_data_valid_arr(idx) := Bool(true)