fix DTLB permissions bug
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1ed89f1cab
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@ -139,15 +139,18 @@ class rocketDTLB(entries: Int) extends Component
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}
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}
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val access_fault_common =
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tlb_hit &&
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val load_fault_common = tlb_hit &&
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((status_s && !sr_array(tag_hit_addr)) ||
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(status_u && !ur_array(tag_hit_addr)) ||
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bad_va)
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val store_fault_common = tlb_hit &&
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((status_s && !sw_array(tag_hit_addr)) ||
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(status_u && !uw_array(tag_hit_addr)) ||
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bad_va)
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io.cpu_resp.xcpt_ld := access_fault_common && (req_load || req_amo)
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io.cpu_resp.xcpt_st := access_fault_common && (req_store || req_amo)
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io.cpu_resp.xcpt_pf := access_fault_common && req_pf
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io.cpu_resp.xcpt_ld := load_fault_common && (req_load || req_amo)
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io.cpu_resp.xcpt_st := store_fault_common && (req_store || req_amo)
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io.cpu_resp.xcpt_pf := load_fault_common && req_pf
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io.cpu_req.ready := (state === s_ready) && !tlb_miss;
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io.cpu_resp.miss := tlb_miss;
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