riscv/rocket-chip
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  • 2c875555a2 Separate exception return control from exception control Andrew Waterman 2015-03-17 00:14:32 -0700
  • f6fe037e30 first cut of merging puts/gets Henry Cook 2015-03-16 23:41:56 -0700
  • 36fc67dc7c cleanup mergeData buffer Henry Cook 2015-03-16 15:06:46 -0700
  • 145e15701e bugfix where an in-progress acquire can be blocked by another acquire tracker being free'd up in between Yunsup Lee 2015-03-16 18:47:16 -0700
  • cf1df2d72a further amo cleanups Henry Cook 2015-03-16 13:27:05 -0700
  • f35a6a574f Add a queue on released data coming in to L2 Henry Cook 2015-03-16 13:25:01 -0700
  • b72230a9f0 PutBlock bugfix Henry Cook 2015-03-16 00:09:55 -0700
  • f6d1a2fb76 No more self-probes required Henry Cook 2015-03-16 00:09:38 -0700
  • 23a6b007c1 Fix BroadcastHub AcquiteTracker allocation bug and clean up tracker wiring Henry Cook 2015-03-15 23:10:51 -0700
  • c03976896e separate queues for resp tag and data Henry Cook 2015-03-15 16:53:15 -0700
  • e85c54cc4b New privileged ISA implementation Andrew Waterman 2015-03-14 02:49:07 -0700
  • 6e540825b2 Use entire 12-bit CSR address Andrew Waterman 2015-03-14 02:15:24 -0700
  • ebbd14254c uncached port should be a HeaderlessUncachedTileLinkIO type Yunsup Lee 2015-03-13 02:12:23 -0700
  • 3a78ca210d bugfix in uncached TL to TL convertors Yunsup Lee 2015-03-12 16:33:35 -0700
  • 51e4cd7616 Added UncachedTileLinkIO port to RocketTile, simplify arbitration Henry Cook 2015-03-12 16:27:40 -0700
  • 8181262419 clean up incoherent and probe flags Henry Cook 2015-03-12 16:22:14 -0700
  • dcc84c4dd3 arbiter probe ready bugfix Henry Cook 2015-03-12 09:33:56 -0700
  • 2c31ed6426 previous bug fix for meta data writeback wasn't quite right Yunsup Lee 2015-03-12 15:34:20 -0700
  • 5e40c8ba77 write back meta data when cache miss even when coherence meta data is clean Yunsup Lee 2015-03-12 14:36:46 -0700
  • 8f8022379c Fix AMO opcode extraction Albert Ou 2015-03-11 23:24:58 -0700
  • f75126c39c Require self probes for all built-in Acquire types Albert Ou 2015-03-11 23:24:58 -0700
  • ea018b3d84 stall rocket decode when not rocc ready Yunsup Lee 2015-03-11 22:33:03 -0700
  • 1aff919c24 added prefetchAck Grant type Henry Cook 2015-03-11 17:32:06 -0700
  • 059575c334 cleanup mergeData and prep for cleaner data_buffer in L2 Henry Cook 2015-03-11 15:43:41 -0700
  • b4ed1d9121 Add builtin prefetch types to TileLink Henry Cook 2015-03-11 14:28:17 -0700
  • 3ab1aca7de L2 subblock access bugfix Yunsup Lee 2015-03-11 01:56:47 -0700
  • e293d89035 fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/ Colin Schmidt 2015-03-10 10:28:05 -0700
  • 17072a0041 L2 Writeback bugfix Henry Cook 2015-03-10 01:15:03 -0700
  • a1f04386f7 Headerless TileLinkIO and arbiters Henry Cook 2015-03-09 16:34:59 -0700
  • 95aa295c39 Use HeaderlessTileLinkIO to cut down on unconnected port errors in VCS Henry Cook 2015-03-09 16:34:43 -0700
  • 002f1a1b39 pin outer finish header Henry Cook 2015-03-09 12:40:37 -0700
  • df79e7ff8d secondary miss bug Henry Cook 2015-03-05 14:40:31 -0800
  • 8e41fcf6fc reduce MemIFTag size, enable non pow2 HellaFLowQueue size Henry Cook 2015-03-05 13:13:12 -0800
  • b36d751250 sret bugfix: bypass arbiter Henry Cook 2015-03-05 13:14:16 -0800
  • 35532420a8 Merge pull request #6 from ccelio/master Henry Cook 2015-03-03 18:01:26 -0800
  • 06dea3790a Removed sret from ptw; sret now comes thru io.cpu to dcache Christopher Celio 2015-03-03 16:50:41 -0800
  • 5d07733057 Removed TLBPTWIO from the io.cpu bundle for icache/dcache Christopher Celio 2015-03-03 16:40:39 -0800
  • 1bed6ea498 New metadata-based coherence API Henry Cook 2015-02-28 17:02:13 -0800
  • 1e0c16c557 new metadata api Henry Cook 2015-02-28 17:00:05 -0800
  • 4f57985198 change organization to riscv Yunsup Lee 2015-02-17 14:43:11 -0800
  • 0a8722e881 bugfix for indexing DataArray of of small L2 Henry Cook 2015-02-17 00:35:18 -0800
  • 0b131173e6 WritebackUnit multibeat control logic bugfix Henry Cook 2015-02-16 10:59:57 -0800
  • 0c66e70f14 cleanup of conflicts; allocation bugfix Henry Cook 2015-02-06 13:20:44 -0800
  • 09cd555f29 Update riscv-tools pointer to prepare for HPCA workshop. Albert Magyar 2015-02-04 13:29:04 -0800
  • 7b86ea17cf rename L2HellaCache to L2HellaCacheBank Henry Cook 2015-02-03 19:37:32 -0800
  • aa46b8b72d Slightly refactor TLBResp Henry Cook 2015-02-03 19:32:08 -0800
  • 3b3250339a Explicitely convert results of Bits Muxes to UInt Stephen Twigg 2015-02-03 18:15:01 -0800
  • 3d35ccd401 Explicitely convert results of Bits Muxes to UInt Stephen Twigg 2015-02-03 18:10:54 -0800
  • 57340be72b doc update Henry Cook 2015-02-02 01:11:13 -0800
  • 6141b3efc5 uncached -> builtin_type Henry Cook 2015-02-02 01:02:06 -0800
  • e6491d351f Offset AMOs within beat and return old value Henry Cook 2015-02-02 00:22:21 -0800
  • 741e6b77ad Rename some params, use refactored TileLink Henry Cook 2015-02-01 20:04:13 -0800
  • 3aa030f960 Support for uncached sub-block reads and writes, major TileLink and CoherencePolicy refactor. Henry Cook 2015-02-01 19:57:53 -0800
  • 7b4e9dd137 Block L2 transactions on the same set from proceeding in parallel Henry Cook 2015-01-06 20:30:52 -0800
  • 973eb43128 state machine bug on uncached write hits Henry Cook 2015-01-05 19:48:49 -0800
  • 00e074cdd9 fixes slight bug for non-power of 2 number of ras entries Scott Beamer 2015-01-29 15:29:25 -0800
  • f58f8bf385 Make L2 data array use a single Mem Henry Cook 2015-01-25 15:37:04 -0800
  • 2a5dd907f5 bump chisel version Scott Beamer 2015-01-06 16:59:10 -0800
  • a98127c09e Merge branch 'ss-frontend' Andrew Waterman 2015-01-04 20:00:08 -0800
  • b70f7683d3 Merge branch 'master' into ss-frontend Andrew Waterman 2015-01-04 19:59:18 -0800
  • 87ad1a5703 More control cleanup Andrew Waterman 2015-01-04 19:46:01 -0800
  • 2aee85cb11 Flush pipeline from MEM stage Andrew Waterman 2015-01-04 16:40:16 -0800
  • 94b75c7cb1 Continue refactoring control Andrew Waterman 2015-01-04 15:21:17 -0800
  • 6181de4cc9 Much refactor, so control Andrew Waterman 2015-01-03 13:34:38 -0800
  • 1cb65d5ec1 %s/master/manager/g Henry Cook 2014-12-29 22:56:18 -0800
  • 9ef00d187f %s/master/manager/g + better comments Henry Cook 2014-12-29 22:55:58 -0800
  • c76b4bc21d TileLink doc Henry Cook 2014-12-29 22:55:18 -0800
  • e62c71203e disconnect unused outer network headers Henry Cook 2014-12-22 18:50:37 -0800
  • 2ef4357ca8 acquire allocation bugfix Henry Cook 2014-12-19 17:39:23 -0800
  • f234fe65ce Initial verison of L2WritebackUnit, passes MiT2 bmark tests Henry Cook 2014-12-19 03:03:53 -0800
  • d121af7f94 Simplify release handling Henry Cook 2014-12-18 17:12:29 -0800
  • 77e5e6b561 refill bug Henry Cook 2014-12-17 19:29:28 -0800
  • bfcfc3fe18 refactor cache params Henry Cook 2014-12-17 14:28:14 -0800
  • 08dcf4c6ca refactor cache params Henry Cook 2014-12-17 14:28:05 -0800
  • ab39cbb15d cleanup DirectoryRepresentation and coherence params Henry Cook 2014-12-15 19:23:13 -0800
  • d29793d1f7 cleanup CoherenceMetadata and coherence params Henry Cook 2014-12-15 19:23:38 -0800
  • d04da83f96 Make data RAMs 1RW instead of 1R1W Andrew Waterman 2014-12-15 17:36:17 -0800
  • 6a8b66231c Add uncached->cached tilelink converter Henry Cook 2014-12-12 12:07:04 -0800
  • 424df2368f 1R/W L2 data array? Henry Cook 2014-12-12 01:11:08 -0800
  • 3026c46a9c Finish adding TLDataBeats to uncore & hub Henry Cook 2014-12-07 03:02:20 -0800
  • 2f733a60db Begin adding TLDataBeats to uncore Henry Cook 2014-12-07 02:57:44 -0800
  • c9320862ae add l2 dmem signal to rocc Henry Cook 2014-12-12 12:05:41 -0800
  • 72ea24283b multibeat TL; passes all tests Henry Cook 2014-12-07 03:09:54 -0800
  • 404773eb9f fix wb bug Henry Cook 2014-12-03 14:22:39 -0800
  • 05b5188ad9 meta and data bundle refactor Henry Cook 2014-11-19 15:55:25 -0800
  • f19b3ca43e Deleted extra spaces at EOL in ctrl.scala Christopher Celio 2014-11-16 22:04:33 -0800
  • 6749f67b7f Fixed BHT update error. Christopher Celio 2014-11-16 22:02:27 -0800
  • a519a43f23 Merge branch 'master' into new-llc Henry Cook 2014-11-12 16:25:25 -0800
  • cb7e712599 Added uncached write data queue to coherence hub Henry Cook 2014-11-12 12:55:07 -0800
  • b7b2923bff Cleanup MSHR internal bundles Henry Cook 2014-11-11 18:18:35 -0800
  • 82155f333e Major tilelink revision for uncached message types Henry Cook 2014-11-11 17:36:55 -0800
  • c9e7874818 Major tilelink revision for uncached message types Henry Cook 2014-11-11 17:36:48 -0800
  • 35553cc0b7 NullDirectory sharers.count fix Henry Cook 2014-11-11 16:05:25 -0800
  • fea31d2167 Significant changes and fixes to BTB for superscalar fetch. Christopher Celio 2014-11-11 03:34:05 -0800
  • bf901e4bca Remove master_xact_id from Release Henry Cook 2014-11-05 13:01:26 -0800
  • 10309849b7 Remove master_xact_id from Probe and Release Henry Cook 2014-11-05 14:21:38 -0800
  • 3be3cd7731 Fixed error with icache/btb resp mask. Christopher Celio 2014-11-03 01:13:22 -0800
  • 27c72e5eed nearly all isa tests pass Henry Cook 2014-10-23 21:50:03 -0700
  • a891ba1d46 more correct handling of internal state Henry Cook 2014-10-21 17:40:30 -0700
  • 170f1fecbc push chisel,rocket,riscv-tools Yunsup Lee 2014-10-21 12:32:31 -0700