riscv/rocket-chip
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Slightly refactor TLBResp

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This commit is contained in:
Henry Cook 2015-02-03 19:32:08 -08:00
parent 3d35ccd401
commit aa46b8b72d
1 changed files with 6 additions and 3 deletions
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9
rocket/src/main/scala/tlb.scala
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@ -76,23 +76,26 @@ class PseudoLRU(n: Int)
}
}
class TLBReq extends TLBBundle {
class TLBReq extends CoreBundle {
val asid = UInt(width = asIdBits)
val vpn = UInt(width = vpnBits+1)
val passthrough = Bool()
val instruction = Bool()
}
class TLBResp(cnt: Option[Int] = None) extends TLBBundle {
class TLBRespNoHitIndex extends CoreBundle {
// lookup responses
val miss = Bool(OUTPUT)
val hit_idx = UInt(OUTPUT, cnt.getOrElse(entries))
val ppn = UInt(OUTPUT, ppnBits)
val xcpt_ld = Bool(OUTPUT)
val xcpt_st = Bool(OUTPUT)
val xcpt_if = Bool(OUTPUT)
}
class TLBResp extends TLBRespNoHitIndex with TLBParameters {
val hit_idx = UInt(OUTPUT, entries)
}
class TLB extends TLBModule {
val io = new Bundle {
val req = Decoupled(new TLBReq).flip