Use HeaderlessTileLinkIO to cut down on unconnected port errors in VCS
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@ -52,3 +52,16 @@ class HellaCacheArbiter(n: Int) extends Module
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io.requestor(i).replay_next.bits := io.mem.replay_next.bits >> UInt(log2Up(n))
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}
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}
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class RocketTileLinkIOArbiter(n: Int) extends TileLinkArbiterLike(n)
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with AppendsArbiterId {
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val io = new Bundle {
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val in = Vec.fill(n){new HeaderlessTileLinkIO}.flip
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val out = new HeaderlessTileLinkIO
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}
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hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
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hookupClientSourceHeaderless(io.in.map(_.release), io.out.release)
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hookupFinish(io.in.map(_.finish), io.out.finish)
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hookupManagerSourceBroadcast(io.in.map(_.probe), io.out.probe)
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hookupManagerSourceWithId(io.in.map(_.grant), io.out.grant)
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}
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@ -45,7 +45,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule
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val io = new Bundle {
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val cpu = new CPUFrontendIO().flip
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val ptw = new TLBPTWIO()
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val mem = new UncachedTileLinkIO
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val mem = new HeaderlessUncachedTileLinkIO
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}
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val btb = Module(new BTB(btb_updates_out_of_order))
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@ -148,7 +148,7 @@ class ICache extends FrontendModule
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val req = Valid(new ICacheReq).flip
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val resp = Decoupled(new ICacheResp)
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val invalidate = Bool(INPUT)
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val mem = new UncachedTileLinkIO
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val mem = new HeaderlessUncachedTileLinkIO
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}
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require(isPow2(nSets) && isPow2(nWays))
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require(isPow2(coreInstBytes))
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@ -273,7 +273,7 @@ class ICache extends FrontendModule
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// output signals
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io.resp.valid := s2_hit
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io.mem.acquire.valid := (state === s_request) && ack_q.io.enq.ready
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io.mem.acquire.bits.payload := GetBlock(addr_block = s2_addr >> UInt(blockOffBits))
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io.mem.acquire.bits := GetBlock(addr_block = s2_addr >> UInt(blockOffBits))
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io.mem.finish <> ack_q.io.deq
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// control state machine
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@ -597,7 +597,7 @@ class HellaCache extends L1HellaCacheModule {
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val io = new Bundle {
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val cpu = (new HellaCacheIO).flip
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val ptw = new TLBPTWIO()
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val mem = new TileLinkIO
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val mem = new HeaderlessTileLinkIO
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}
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require(params(LRSCCycles) >= 32) // ISA requires 16-insn LRSC sequences to succeed
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@ -802,7 +802,7 @@ class HellaCache extends L1HellaCacheModule {
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mshrs.io.req.bits.data := s2_req.data
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when (mshrs.io.req.fire()) { replacer.miss }
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io.mem.acquire <> DecoupledLogicalNetworkIOWrapper(mshrs.io.mem_req)
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io.mem.acquire <> mshrs.io.mem_req
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// replays
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readArb.io.in(1).valid := mshrs.io.replay.valid
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@ -815,7 +815,7 @@ class HellaCache extends L1HellaCacheModule {
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// probes and releases
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val releaseArb = Module(new LockingArbiter(new Release, 2, outerDataBeats, (r: Release) => r.hasMultibeatData()))
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DecoupledLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release
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releaseArb.io.out <> io.mem.release
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val probe = DecoupledLogicalNetworkIOUnwrapper(io.mem.probe)
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prober.io.req.valid := probe.valid && !lrsc_valid
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@ -42,8 +42,8 @@ class RoCCInterface extends Bundle
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val interrupt = Bool(OUTPUT)
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// These should be handled differently, eventually
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val imem = new UncachedTileLinkIO
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val dmem = new TileLinkIO
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val imem = new HeaderlessUncachedTileLinkIO
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val dmem = new HeaderlessTileLinkIO
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val iptw = new TLBPTWIO
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val dptw = new TLBPTWIO
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val pptw = new TLBPTWIO
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@ -14,7 +14,7 @@ case object BuildRoCC extends Field[Option[() => RoCC]]
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abstract class Tile(resetSignal: Bool = null) extends Module(_reset = resetSignal) {
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val io = new Bundle {
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val tilelink = new TileLinkIO
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val tilelink = new HeaderlessTileLinkIO
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val host = new HTIFIO
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}
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}
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@ -39,10 +39,10 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
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core.io.imem <> icache.io.cpu
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core.io.ptw <> ptw.io.dpath
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val memArb = Module(new TileLinkIOArbiterThatAppendsArbiterId(params(NTilePorts)))
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val memArb = Module(new RocketTileLinkIOArbiter(params(NTilePorts)))
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io.tilelink <> memArb.io.out
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memArb.io.in(0) <> dcache.io.mem
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memArb.io.in(1) <> TileLinkIOWrapper(icache.io.mem)
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memArb.io.in(1) <> HeaderlessTileLinkIOWrapper(icache.io.mem)
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//If so specified, build an RoCC module and wire it in
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params(BuildRoCC)
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@ -52,7 +52,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
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core.io.rocc <> rocc.io
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dcIF.io.requestor <> rocc.io.mem
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dcArb.io.requestor(2) <> dcIF.io.cache
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memArb.io.in(2) <> TileLinkIOWrapper(rocc.io.imem)
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memArb.io.in(2) <> HeaderlessTileLinkIOWrapper(rocc.io.imem)
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memArb.io.in(3) <> rocc.io.dmem
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ptw.io.requestor(2) <> rocc.io.iptw
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ptw.io.requestor(3) <> rocc.io.dptw
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